PCB Design Guidelines for Ensuring EMC

Modern PCB design must take electromagnetic compatibility (EMC) into account from the very beginning. Below is a comprehensive set of rules and recommendations aimed at reducing electromagnetic interference (EMI) and improving immunity to it.

The guidelines are organized by topic — from high-power supplies and high-speed digital signals to sensitive analog circuits, RF designs, and ESD protection measures.

Each rule includes a clear title, a detailed explanation with the underlying physics (electric fields, magnetic fields, differential currents, radiation), the purpose of the recommendation, situations where it becomes especially critical, and examples of correct implementation or common mistakes.

At the end of the document, you’ll find references to authoritative sources: engineering books, application notes, manufacturer guidelines, and discussions from technical forums.

1. Power Supplies and Power Circuits (DC/DC Converters, Gate Drivers, H-Bridges, Motor Drivers)

   
   

   Power circuits — such as switching buck/boost regulators, transistor gate drivers, and motor bridge inverters — are among the primary sources of noise and interference on a PCB. Fast current transitions (high di/dt) and rapid voltage changes (high dv/dt) generate strong magnetic and electric fields that can lead to radiated emissions and functional disturbances.

   Below are guidelines aimed at minimizing radiation and improving the noise resilience of power circuits:

Rule Minimize the area of “hot” current loops (high di/dt loops)

• Explanation (physical basis) In a switching converter, the main source of EMI is the “hot” current loop — the part of the circuit where current is interrupted by the switching transistor and flows through the input capacitor.

  If this loop is long and spread out, it radiates a strong magnetic field (H-field), which is proportional to both the loop area and the magnitude of the alternating current. A larger loop area means higher loop inductance and stronger radiation.

  By minimizing the loop area, you reduce the loop inductance and significantly decrease the radiated magnetic field (since the field strength is approximately proportional to current multiplied by loop area).

• Goal and effect Reduction of magnetic field radiation and mitigation of differential-mode EMI. A smaller loop generates weaker interference in both the near field and the far field. Operational stability also improves, with less voltage droop and reduced noise at the output.

• When it’s especially important A fundamental principle for all DC/DC converters, MOSFET/IGBT drivers, and any circuits that switch high currents. It becomes especially critical when meeting CISPR 25 requirements for automotive equipment or FCC Class B limits, where high-frequency emissions from power electronics must be kept to a minimum.

• Implementation examples / common mistakes Implementation: place the input bypass capacitor as close as possible to the transistor and diode/switch pins, forming a compact power loop.

  Use a ground polygon or solid ground plane directly beneath this loop on an adjacent layer for shielding (this creates a current “image” that counteracts the magnetic field).

  Common mistake: routing a long trace from the capacitor to the switching device, creating a large loop. This leads to strong radiation and often results in failing EMC radiated emissions tests.

Rule Place decoupling capacitors directly next to the power pins (VIN, VOUT, driver supply).

• Explanation (physical basis) Input and output capacitors create local return paths for alternating currents. The input capacitor must handle the entire AC current of the switching device and close the loop to ground locally, preventing the current from flowing through long traces.

  Small, low-inductance SMD capacitors should be placed closest to the pins (especially for high-frequency noise), while larger capacitors can be positioned slightly farther away. This reduces parasitic inductance in the power path and minimizes voltage spikes during switching transitions.

• Goal and effect Providing a low-impedance source for switching elements at high frequencies.

  Reducing radiated interference and voltage spikes on transistors (additional dv/dt caused by trace inductance).

  Improving power supply noise immunity (resistance to external disturbances).
  

• When it is especially important Always in switching converters (buck, boost, flyback, etc.). It becomes especially critical at higher supply voltages and switching frequencies (sharper edges mean stricter decoupling requirements).

  For gate drivers and bridge circuits, the local driver supply (for example, the bootstrap capacitor charge path) must also form a minimal loop.
  

• Implementation examples / common mistakes Implementation: place a ceramic capacitor (for example, 0.1 µF X7R, 16 V, 0402) directly between the controller’s VIN and GND pins, as close to the IC leads as physically possible. Connect it to ground using multiple parallel vias placed right at the pad.

  If needed, use several capacitors of different values in parallel (for example, 0.1 µF + 4.7 µF): the smaller one “catches” the high-frequency components, while the larger one stabilizes the lower-frequency content.

  Common mistake: using a single electrolytic input capacitor located several centimeters away. This results in a large ESL, sharp input-voltage bouncing, and strong electromagnetic radiation on every switching transition.

Rule Keep the “floating” switching node compact and away from sensitive circuits (minimize the copper area of the SW node).

• Explanation (physical basis) At the node between the transistor and the inductor (or the collector/drain node in a bridge stage), the voltage has a very high dv/dt, making it a strong source of alternating electric field (E-field). If the copper pour for this node is spread over a large area, it behaves like an antenna: it radiates electromagnetic interference and can capacitively couple noise into nearby circuits.

  Keeping this node’s area small reduces parasitic capacitance to other nets and decreases E-field radiation.

• Goal and effect Reduction of electric field radiation (especially at high frequencies — the harmonics of fast edges).

  Parasitic (capacitive) coupling between this node and the rest of the circuit is reduced, which minimizes interference injected into sensors, reference voltages, and similar sensitive nodes.

  As a result, the likelihood of passing radiated EMC tests increases, and overall signal integrity is preserved.

• When it is especially important In high-voltage conversion stages (for example, 48 V to 5 V, or high-power MOSFET drivers), the voltage at the switching node can change by tens of volts within nanoseconds. In such cases, the high dv/dt becomes particularly critical.

  This is also especially important in designs where sensitive analog circuitry is located nearby — for example, if a DC/DC converter is placed close to an ADC or an RF section. In these situations, minimizing the SW copper area is essential.
  

• Implementation examples / common mistakes Implementation: limit the copper area at the transistor output (the SW node) to the pad itself and a short connection to the inductor. Do not pour a large polygon around this node across multiple layers.

  Where possible, shield the node — for example, by adding a copper “cap” above it (left unconnected) or using a shielding can tied to ground — to confine the E-field locally.

  Common mistake: “triangle” routing, where the transistor, diode, and inductor are connected with very wide traces/pours spread across half of the board. This creates capacitive coupling of switching pulses into surrounding circuitry and produces strong high-frequency interference, including RF noise.

Rule Separate the power “noisy” ground and the control ground, connecting them at a single point (star connection).

• Explanation (physical basis) Ground areas that carry pulsed power return currents (DC/DC input currents, motor currents through shunts, etc.) become very noisy — voltage spikes develop on them due to their own inductance and resistance. If sensitive circuits (PWM controller, voltage reference, current sensors) are tied to the same ground, this noise shifts their reference level.

  The rule is to provide a separate local ground pour or ground region for low-power controllers and sensors that does not share the high-current return path, and then connect it to the main ground at a single point (typically near the power entry point or at the IC’s AGND pin). This way, noisy currents do not flow through the “quiet” ground area

• Goal and effect Prevents contamination of reference and signal circuits by ground noise (reduces common-mode interference). As a result, PWM controllers, ADCs, and amplifiers operate more stably, and radiation is reduced: by localizing current paths, large ground loops are avoided.

• When it is especially important When a single device combines high-power and sensitive circuitry. For example, in a dashcam power supply: a switching converter together with a highly sensitive GPS receiver. Or in a motor control board: a MOSFET driver alongside a microcontroller with an ADC. In such cases, ground separation is critical for EMC.

  It is especially important in audio amplifiers: the amplifier ground must connect to the power ground at a single star point; otherwise, hum and noise will appear.
  

• Implementation examples / common mistakes Implementation: on a multilayer board, a solid ground plane can still be used, but the areas should be functionally separated. Under the power transistor and input capacitor — use a power ground (PGND) region. Under the PWM controller and its surrounding circuitry — use a signal ground (SGND) region.

  Connect these ground regions with a narrow link (a 0 Ω resistor or a single via) at a point where noise is minimal — for example, near the negative terminal of the output capacitor or at the controller’s GND pin.

  Common mistake: using a single unified ground without considering current paths — high current from the MOSFET flows beneath the controller IC, creating ground shifts of up to 0.5 V at the controller ground, causing sensor malfunction.

  Another mistake: connecting the separated grounds at multiple points (forming a ground loop). This can lead to even higher radiated emissions.

Rule

Do not use thermal reliefs on critical high-current nodes.

• Explanation (physical basis) Thermal reliefs are narrow spokes connecting a pad to a copper polygon, intended to make soldering easier. However, they introduce additional inductance and resistance.

  In power circuits (such as the ground of a switching device or capacitor terminals), this is unacceptable because it increases impedance and impairs the rapid return of high-frequency currents to ground.

  Using thermal relief on an input ground pad can increase the effective current loop area and lengthen the return path.

  
  

• Goal and effect Providing minimum-impedance connections within high-current switching loops. As a result, high-frequency noise and interference are reduced. In addition, voltage spikes on components decrease (since L × di/dt is lower).

  
  

• When it is especially important At power connectors, the terminals of power capacitors (Cin, Cout), transistors, and shunts — especially where high-frequency currents are present.

  For example, a 10 µF 50 V ceramic input capacitor should not use a thermal relief connection to ground — otherwise, the benefit of its low ESL is effectively lost.

  
  

• Implementation examples / common mistakes Implementation: in the PCB CAD tool settings, disable thermal relief for specific nets or polygons (such as GND and power rails), or for selected components. Use solid connections — the pad should connect to the polygon over its entire perimeter.

  Soldering may require a higher temperature, but this is the cost of achieving proper EMC performance.

  Common mistake: leaving thermal relief enabled by default for all components. As a result, decoupling capacitors end up connected to ground through narrow spokes, and high-frequency noise is not effectively shunted but instead radiates.

Rule Use a multilayer PCB with tightly coupled power and ground planes.

• Explanation (physical basis) Between solid planar power and ground layers, a distributed capacitor is formed. When the spacing is small (for example, 0.1–0.2 mm between VCC and GND), a significant parallel capacitance appears (on the order of tens of picofarads per square centimeter), which acts as natural high-frequency decoupling.

  In addition, closely spaced planes form a low-radiation transmission structure: the electromagnetic field generated by supply currents is confined within the layer stack.

  Conversely, if the planes are spaced far apart (thicker dielectric), the loop inductance between them increases at high frequencies, and their ability to suppress noise degrades.

• Goal and effect Reduction of power distribution network (PDN) impedance at high frequencies and improved filtering of supply noise.

  In EMC terms, this means lower radiation from the planes (both as a “slot antenna” and as a conductive antenna).

  Immunity to interference is also improved — the planes act as shields against electromagnetic fields.

• When it is especially important When designing boards with high-density digital circuits (MCUs, FPGAs, processors) and power converters, a stackup of at least four layers is recommended, including one solid ground plane and one or two power planes.

  This becomes especially important at switching frequencies above 1 MHz and with fast signal edges — closely spaced planes help confine harmonics up to hundreds of MHz within the PCB structure.

  To meet stringent standards (such as CISPR 25 Class 5 or FCC Class B), it is often not feasible to pass without a multilayer stackup.

• Implementation examples / common mistakes Implementation: example stackup — top layer: signal; layer 2: solid ground; layer 3: power; bottom layer: signal.

  The spacing between layer 2 and layer 3 should be as small as possible (for example, 0.2 mm of FR4). This creates a planar capacitor between VCC and GND.

  For high-frequency supply domains (such as an FPGA core), special materials or additional closely spaced plane pairs are sometimes used to increase interplane capacitance.

  Common mistake: trying to implement a complex design on a 2-layer board without a solid ground plane. This results in large current loops, no interplane decoupling, and EMC failure (the board effectively behaves like an antenna).

  Another example: using a thick dielectric (>1 mm) between power and ground for mechanical strength, sacrificing EMC performance in the process.

Rule Use shielded components and components with low parasitic magnetic fields.

• Explanation (physical basis) A common example is a shielded inductor in a switching regulator. An unshielded inductor radiates a strong magnetic field around it, causing coupling into nearby loops and components.

  A magnetic shield (such as a ferrite cap around the inductor) significantly reduces the stray H-field.

  Similarly, using IC packages with low lead inductance (for example, flip-chip or WLCSP) reduces parasitic inductance and, as a result, decreases both self-generated voltage spikes and susceptibility to coupled noise.

• Goal and effect Limiting the spread of the magnetic field in space means lower differential-mode interference (since mutual inductive coupling between circuits is reduced).

  In addition, shielded inductors confine the magnetic flux within the core, making them less likely to excite common-mode currents on the chassis.

  Low parasitic inductance in IC packages results in smaller voltage overshoots and less noise — which in turn means the circuit emits fewer high-frequency harmonics.

• When it is especially important Recommended for noise-sensitive applications: automotive electronics (radios, audio systems), RF devices with onboard DC/DC converters (such as Wi-Fi modules powered by a buck converter), and precision measurement equipment.

  If your converter is located near an antenna or an input amplifier, a shielded inductor is mandatory.

  For IC package selection: for high-frequency controllers, QFN or LGA packages are preferable to long-leaded SOIC packages.

• Implementation examples / common mistakes Implementation: replace an open-wound inductor with a shielded equivalent (with a ferrite cover or molded powder core). For example, use a molded inductive “cube” instead of a toroidal coil.

  Use low-profile SMD capacitors (e.g., X7R 0805) instead of radial electrolytics, whose leads add inductance (~5–10 nH).

  Common mistake: cost-cutting by selecting inexpensive unshielded inductors — this can lead to failure in radiated emission testing. Another example is using diodes or MOSFETs in packages with long leads, which introduce parasitic inductance and result in stronger high-frequency emissions during switching.

Rule Add damping networks (RC snubbers, gate resistors) to smooth switching edges.

• Explanation (physical basis) Excessively fast voltage and current edges are a primary cause of radiated emissions. Even increasing the rise/fall time by a few tens of percent can significantly reduce the harmonic content (less energy at high frequencies).

  A gate resistor in a MOSFET slows the current rise (by limiting di/dt), while an RC network (snubber) at the switching node damps resonant oscillations in the circuit, dissipating their energy as heat.

  As a result, high-frequency spikes and ringing harmonics are reduced — these are typically the components that cause EMC test failures.

  
  

• Goal and effect Reduce the amplitude and steepness of the high-frequency components of switching transitions. This lowers radiated EMI (especially in the 30–300 MHz range, where trace lengths can approach quarter-wave resonance) and suppresses spectral peaks.

  It also improves reliability — with reduced voltage overshoot on switching devices and less electromagnetic coupling into neighboring circuits.
  

• When it is especially important When compliance with the strictest EMI limits is required, or when noise cannot be controlled otherwise.

  Example: a 1 MHz power module fails Class B radiated emission limits — adding a snubber across the diode cuts the 100 MHz peak in half.

  In a motor driver operating with very fast edges that cause radio interference, inserting a 10 Ω resistor in the IGBT gate slightly slows the transition and resolves the issue.

  
  

• Implementation examples / common mistakes Implementation: an RC snubber is typically placed between the SW node and ground. A small network (for example, 100 Ω + 1000 pF) is selected experimentally by observing voltage spikes on the transistor with an oscilloscope.

  A gate resistor is usually chosen in the range of 4.7 to 47 Ω to find a balance between switching speed and noise. In some cases, a diode is placed in parallel with the resistor to set different turn-on and turn-off speeds.

  Common mistake: neglecting damping — the circuit operates at the maximum possible switching speed, leading to strong high-frequency ringing and causing the device to radiate interference into the surrounding environment.

Explanatory notes:

In power circuits, magnetic fields (H-fields) dominate due to the low impedance of the loops and the large currents involved. Therefore, minimizing the area of current loops is the primary measure. As commonly noted, every conductor together with its return path forms a loop antenna that radiates EMI; reducing the loop area directly reduces radiation.

Using a solid ground plane beneath power traces allows the return current to flow directly under the signal path, inherently minimizing the EMI loop. This is a universal rule — the physics works in your favor: the ground plane attracts and closes the field lines. For example, moving to a multilayer PCB with a continuous ground plane often resolves interference issues that cannot be solved on a two-layer board.

In power electronics, it is also critical to distinguish between differential-mode and common-mode interference. Differential-mode noise (conducted within the power-to-ground loop) is mitigated by minimizing loop areas, applying shielding, and using filtering components (capacitors, ferrites). Common-mode noise — where the entire system “floats” relative to the external environment — requires symmetry and proper grounding.

For example, if long power cables act as antennas, a common-mode choke (CM choke) or filter is added to suppress common-mode currents. The discussion above focuses on differential-mode mitigation within the PCB. Common-mode effects become particularly significant in the presence of cables — this will be addressed later in the section on ESD and external interfaces.

Finally, at the system level, careful component placement is essential. Components should be grouped by function — power stages kept away from highly sensitive circuitry. The overall PCB topology strongly affects EMC. For example, placing the DC/DC converter as close as possible to the power input connector prevents its noise from spreading across the board. Similarly, positioning the motor driver close to the motor connector reduces loop area and radiated emissions.

In demanding applications with strict compliance requirements, it may be necessary to allocate space for a shielding enclosure over the power section. This mechanical solution is often required to meet standards such as CISPR 25 Class 5 (automotive).

2. High-Speed Digital Interfaces (USB, HDMI, Ethernet, DDR, etc.)

High-speed signals produce fast edges and a rich harmonic spectrum that can cause radiation both along conductors and into free space. At the same time, they are sensitive to interference, which manifests as signal integrity degradation and transmission errors.

When routing such lines, signal integrity (SI) and EMC must be addressed together — these areas are closely interconnected.

Below are the key design rules for USB 2.0/3.0, HDMI (TMDS), Ethernet (100BASE-T/1000BASE-T), high-speed memory buses (DDR), and other digital interfaces operating at tens of MHz and above.

Rule Routing with controlled impedance and a continuous reference ground plane.

• Explanation (physical basis) Long high-speed traces on a PCB behave as transmission lines at high frequencies. An impedance mismatch leads to reflections, standing waves, and amplification of certain frequencies — which can result in resonant radiation.

  The solution is to calculate trace width and spacing to the reference layer (ground or power) to achieve the required characteristic impedance (for example, 50 Ω single-ended, 90 Ω differential for USB/HDMI, 100 Ω differential for Ethernet).

  A solid copper plane beneath the trace acts as the reference conductor, allowing the return current to flow along the shortest path. Breaks or gaps in the reference plane force the return current to detour, increasing the loop area — and therefore increasing radiation.

• Goal and effect Reduction of reflections and prevention of resonant noise amplification.

  Controlled impedance is fundamental for signal integrity, but it is equally important for EMC: eliminating standing waves reduces the likelihood of strong radiation at frequencies corresponding to λ/2 of the trace length.

  A continuous reference ground plane beneath a differential pair keeps the electromagnetic field confined between the conductors and the ground, minimizing radiation into the surrounding space.

• When it is especially important Mandatory for any lines with fast edges: clock signals above 50 MHz, USB High Speed (480 Mbps), HDMI, PCIe, DDR — essentially anything with a spectral peak above 100 MHz.

  Without proper impedance control, such traces can radiate like quarter-wavelength antennas.

  In addition, meeting FCC/CISPR limits becomes difficult if the main system clock (for example, 200 MHz) is not impedance-controlled — it will radiate at its harmonic frequencies.

• Implementation examples / common mistakes Implementation: use a multilayer PCB where signal traces run on a layer adjacent to a solid ground plane.

  Calculate trace width and spacing to the reference plane using an impedance calculator or field solver to achieve the required characteristic impedance.

  For example, a USB D+/D− differential pair on a 1.6 mm PCB can achieve 90 Ω differential impedance with trace widths of about 0.3 mm and spacing of approximately 0.2 mm, routed over a solid ground plane at a separation of around 0.25 mm (depending on the stackup and dielectric properties).

  Common mistake: routing high-speed signals on a two-layer board without a continuous ground plane — the impedance becomes uncontrolled, leading to reflections and overshoot. Another mistake is routing these signals across gaps in the ground plane (for example, over a connector cutout or slot) — the return current is forced to detour, and radiation increases significantly.

Rule Route differential pairs close together and symmetrically.

• Explanation (physical basis) A differential signal consists of two conductors carrying equal and opposite phases. Ideally, they generate electromagnetic fields that cancel each other: the far-field electric and magnetic radiation remains small because the currents are equal in magnitude, opposite in direction, and closely spaced.

  As a result, a differential pair mainly generates common-mode radiation only when imbalance occurs. The closer and more uniformly the pair is routed, the more effectively the external fields cancel, confining the electromagnetic field between the conductors.

  External interference tends to couple equally into both conductors (common-mode) and is then rejected by the differential receiver.

  However, even slight imbalance (timing skew, asymmetrical geometry) produces a common-mode component — effectively turning the differential pair into two separate radiating antennas.

  Therefore, maintaining equal length and consistent parallel routing is critical.

• Goal and effect Minimize both radiation and susceptibility of differential lines. A properly routed differential pair radiates very little in differential mode, and its common-mode component remains low, making it easier to pass EMC tests.

  It is also less susceptible to external noise — common-mode interference induced on both conductors will be rejected by the differential receiver.

  The result is cleaner signal integrity and fewer radiated emission issues.

• When it is especially important Applies wherever paired lines are used: USB, HDMI (TMDS pairs), DisplayPort, LVDS, Ethernet twisted pairs, balanced audio lines, and differential clocks (such as LVDS or CML clocks for high-speed ADCs).

  For DDR interfaces (which are mostly single-ended, except for clocks), close pairing is less applicable. In that case, maintaining proximity to a solid ground reference and proper spacing between traces becomes more important.

• Implementation examples / common mistakes Implementation: route the differential pair side by side along its entire length, maintaining constant spacing (except for minor, smoothly shaped deviations to avoid obstacles — keep these to a minimum).

  Match the trace lengths — the difference should not exceed about 5 mil (0.127 mm), and even tighter for gigabit data rates, to avoid skew.

  Terminate the pair properly if required (for example, 100 Ω between the lines at the receiver, or using a differential transformer where applicable).

  Common mistake: one trace detours around a connector while the other takes a direct path — this creates a length mismatch, timing skew, and strong radiation, almost as if they were separate single-ended lines.

  Another example: spreading the pair apart “for easier routing” — this reduces field cancellation, creates a larger loop, and increases radiation.

Rule Avoid unnecessary discontinuities, transitions, and breaks (minimize vias and connectors).

• Explanation (physical basis) Every transition (via, connector, layer change without a continuous return plane) introduces a discontinuity, leading to partial signal reflection and radiation.

  As high-frequency current passes through a via, it can excite parasitic modes (for example, between the via barrel and nearby planes), and any unused portion of the via (a stub) can behave like a quarter-wave resonator.

  Ideally, a high-speed signal should be routed entirely on a single layer over a continuous ground plane, without interruptions. If a via is necessary, place a nearby ground via to maintain the return path (for differential pairs, place a grounded via close to each trace).

  Both traces in a differential pair must have the same number of vias to avoid introducing delay mismatch and unequal losses.

• Goal and effect Minimize parasitic radiation at transitions and prevent signal degradation.

  Proper control of transitions keeps the signal energy confined within the transmission path (instead of radiating into free space) and maintains effective return-current shielding.

  As a result, resonant peaks are reduced — for example, when the via stub length equals λ/4, it can radiate strongly; trimming the stub or effectively grounding it eliminates this effect.

• When it is especially important Especially critical at very high data rates: PCIe Gen3/4, USB 3 (5–10 Gbps), HDMI 2.0 (6 Gbps) — at these speeds, each via can introduce noticeable signal distortion.

  The same applies to DDR4/DDR5, since their harmonic content reaches several GHz.

  At lower speeds (USB 2.0 at 480 Mbps, Ethernet at 125 MHz), the impact is more tolerable, but unnecessary transitions should still be avoided, as cumulative effects can still cause test failures.

• Implementation examples / common mistakes Implementation: when planning the layer stack, try to keep critical signals on as few layers as possible. For example, place the entire USB hub and its connectors on the top layer so that the USB differential pairs do not transition up and down between layers.

  If a layer transition is unavoidable, use backdrilling — removing the unused portion of the via that extends beyond the last connected layer. This eliminates the stub and removes its resonant behavior.

  Also use coaxial connectors or connectors with controlled impedance transitions (for example, HDMI connectors are designed with specific contact geometry).

  Common mistake: using a low-cost pin header to connect HDMI signals between two boards — the pins create impedance discontinuities, the signal becomes distorted, and radiated emissions increase.

  Another example: long “hanging” via stubs — the signal transitions to layer 2, but the via barrel continues down to layer 8, acting like an antenna stub. At GHz frequencies (quarter-wavelength resonance), this can produce a radiation peak that causes EMC test failure.

Rule Route signals with crosstalk considerations in mind.

• Explanation (physical basis) At frequencies in the tens to hundreds of MHz, closely spaced parallel traces create parasitic capacitance and mutual inductance. A fast edge on one line will capacitively couple a transient into the adjacent line.

  This appears as signal degradation (edge jitter, undershoot) and can also contribute to radiation, since coupled noise is generated.

  The 3W rule applies: the center-to-center spacing between adjacent traces should be at least three times the trace width to significantly reduce coupling.

  It is also recommended that critical signals do not run in parallel for long distances — it is better to separate them with a ground trace or route them on different layers.

  Signals crossing at 90° on different layers have much weaker coupling (their magnetic fields are orthogonal, reducing interaction).
  

• Goal and effect Reduction of parasitic coupling and prevention of intermodulation between different frequencies.

  If strong noise is not coupled into adjacent signal paths, overall radiation remains lower.

  In RF receivers, this is also critical: crosstalk can transfer interference into another frequency channel.

• When it is especially important On memory buses (DDR), parallel address and data lines can experience significant crosstalk, which is why signals are often interleaved with ground (“every 8th trace is ground,” for example).

  In long interface bundles (such as multiple MIPI DSI or CSI lanes), crosstalk control is critical.

  From an EMI perspective, any two long parallel traces can behave like a dipole antenna, coupling into each other and increasing radiation. Such structures should be avoided whenever possible.

• Implementation examples / common mistakes Implementation: follow the “3W rule” — for example, if a trace is 4 mil wide, the spacing to the nearest parallel trace should be at least 12 mil.

  Alternatively, insert a ground-connected trace between them (a so-called guard trace) — it acts as a shield and returns the induced current to ground.

  Use perpendicular routing on adjacent layers: if signals on the top layer run horizontally, then on the next inner layer they should run vertically. This minimizes long parallel coupling sections.

  Common mistake: routing all eight memory address lines side by side in a tight bundle — when one line switches, noise appears on the adjacent lines, leading to errors and increased radiation.

  Another example: tightly routing multiple differential pairs next to each other without separation — the pairs can couple (especially if operating at different frequencies). Adding a ground pour between them can help reduce interaction.

Rule Use proper termination and filtering for external interfaces.

• Explanation (physical basis) Many high-speed interfaces connect to cables (USB, HDMI, Ethernet). A cable is an efficient radiator, so it is essential to suppress high-frequency currents on it.

  Proper termination (resistive, transformer-based, or RC) prevents reflections at the board-to-cable interface, reducing radiation at the transition point.

  Common-mode chokes are placed in differential lines before the connector to suppress common-mode currents — that is, currents flowing equally on both conductors and coupling into the cable as radiation. These chokes pass the differential signal (the useful signal) while blocking noise that would otherwise radiate through the cable.

  In addition, ESD protection (TVS diodes) is required on these lines. Beyond protection, their parasitic capacitance provides slight high-frequency filtering, and the TVS itself shunts high-energy transients (for example, from ESD events) directly to ground, preventing radiation and damage.

• Goal and effect Ensures compliance with EMC standards when cables are connected. A large portion of radiated emission test failures is caused by cables radiating noise coupled from the PCB.

  Proper termination and filtering eliminate the currents that turn the cable into an antenna. At the same time, they help suppress incoming external interference, preventing it from entering the board.

• When it is especially important USB: a common practice is to place a 4-line common-mode choke on the D+/D− pair (for USB 2.0). For USB 3.0, common-mode chokes are used on the two SuperSpeed differential pairs to reduce radiation around 240 MHz and its harmonics (USB 2.0 clock at 480 MHz).

  Ethernet: the magnetics (transformers) integrated into the connector provide galvanic isolation and common-mode filtering. In addition, 49.9 Ω termination resistors on the differential pairs help match the impedance.

  HDMI: TMDS lines are 100 Ω differential pairs; mini common-mode chokes and ESD protection devices (such as TPD12S series chips) are often added.

  DDR: although there is no external cable on the internal memory bus, termination resistors are used to absorb reflections. This is primarily a signal integrity measure, but it also reduces the potential for radiation at the end of the line.

• Implementation examples / common mistakes Implementation: follow reference designs and populate the specified termination components (resistors, capacitors) and dedicated filter parts.

  For example, the Bob Smith termination in Ethernet connects the center taps through capacitors to chassis/ground, reducing common-mode noise on the cable.

  For USB, small-signal ferrite beads (around 100 Ω @ 100 MHz) are often placed in the VBUS and/or GND lines near the connector to block high-frequency noise on the supply path.

  Common mistake: missing or incorrect termination. For instance, the HDMI cable shield is not connected to the PCB ground properly, but is left “floating” or connected through a long trace — the whole system then behaves like an antenna.

  Another mistake is leaving ESD diode footprints unpopulated: during an ESD strike, the transient goes straight into the IC, causing malfunctions and generating a broadband radiated burst because it was not shunted to ground at the connector.

Explanatory notes:  High-speed digital traces can act both as sources of radiation and as points where interference is received. Using differential signaling significantly improves robustness: as described, tightly coupled differential conductors keep most of their electromagnetic field confined between them, which reduces radiation.

But a differential pair is not a cure-all — if it is unbalanced (unequal length, routed far apart, or driven by an imbalanced transmitter), a common-mode component appears, effectively equivalent to a single noisy conductor. Therefore, careful length matching and symmetry are not only about propagation delay and timing, but also about EMC.

Return-path continuity is extremely important. For example, if a clock signal crosses a break in the ground plane (say, at a transition between modules or near a power connector where the ground is split), its return current is forced to detour, creating a large loop. That is a reliable recipe for radiation. The correct approach is either to avoid such breaks or to provide a bridge: for instance, tie the split grounds together along the signal path with a 0.1 µF capacitor (at high frequencies it behaves like a jumper), or place ground vias nearby. The latter is via stitching — an array of vias that “stitches” the ground copper together along the edge of the split. These vias provide a nearby return path, reducing the loop area.

It is also worth mentioning the “20H rule” — a historical recommendation to pull the edge of the power plane inward relative to the ground plane by 20× the dielectric thickness, to reduce edge-field radiation. More recent studies suggest that the 20H effect is minor below 1 GHz; instead, it is generally more effective to limit board/plane dimensions and place decoupling capacitors around the perimeter. Along the board edge, designers often add a “ground ring” — a ground perimeter trace with frequent vias — which provides shielding against ESD and helps prevent fields from spreading outward.

External interfaces (USB, HDMI, etc.) require attention to connector mechanics. Plugs are typically metal-shielded; it is important to connect that shield to the PCB ground plane at the entry point (often through multiple solder tabs). For example, the USB connector shell should contact the ground copper — then the connector shield becomes a continuation of the PCB’s shield and helps dump interference to ground. With HDMI and similar interfaces, there are multiple GND pins around the signal pins, and these should be tied directly into ground so that each differential pair has a nearby return path. This is sometimes referred to as frequent grounding: it reduces the inductance of the connection between the cable shield and the device ground. Without it, emissions at the interface can increase.

And, of course, trace lengths and impedance control matter for EMC as well: the goal is not only to meet timing, but also to avoid unnecessary resonant trace segments. For example, if the board is large and a clock trace is 10 cm long, it can become a quarter-wave resonator around ~300 MHz. Where possible, shorten such runs or add absorbers (resistors, ferrites). In DDR designs, a “fly-by” topology with termination at the end is sometimes used — it damps reflections and reduces ringing at the end of the bus.

3. Analog and Sensitive Circuits (ADCs, Voltage References, Low-Noise Amplifiers)

Sensitive analog circuits are vulnerable to electromagnetic interference and can themselves be sources of low-frequency coupling and noise. The goal of PCB design is to protect them from digital and power-stage noise, ensure stable reference nodes, and reduce pickup of unintended signals.

Proper grounding and shielding are especially important here. The following rules apply:

Rule Separate analog and digital grounds, connecting them at a single point (star connection).

• Explanation (physical basis) Mixed-signal systems contain both analog nodes (operational amplifiers, ADCs, sensors) and digital circuitry (microcontrollers, logic). If they share a single solid ground plane, both smooth analog currents and sharp digital switching currents flow through it. The latter create ground noise (voltage drops) that can distort analog measurements.

  Separating AGND (analog ground) and DGND (digital ground) is a classic approach: the grounds are implemented as separate polygons, connected at only one point (typically beneath the ADC or the voltage reference).

  In this configuration, digital return currents flow in the digital ground region, and analog currents return through the analog ground, minimizing interaction between them.

  If a signal crosses between analog and digital domains (for example, an ADC output going to a microcontroller), it should be routed across the ground connection point so that a large return-current loop is not formed.

• Goal and effect Provide a “clean” reference potential for analog circuits and minimize the shared ground impedance between digital and analog sections.

  This improves measurement accuracy (no ground shifts), reduces background noise in ADCs/DACs, and prevents digital noise from coupling into analog circuitry.

  From an EMC perspective, it reduces parasitic radiation caused by uncontrolled current flow across the board and lowers susceptibility — for example, preventing digital switching spikes from appearing at an amplifier input.

• When it is especially important In all systems that include highly sensitive analog sections: precision sensors, high-resolution ADCs, audio paths with microphones and amplifiers, and circuits handling very small signals (down to nanovolts).

  For example, in an oscilloscope front-end board, the input amplifiers are separated from the digital ground and connected at a single star point near the input connector.

  Or in a microcontroller system with an integrated ADC and high-current digital logic — if grounding is poorly managed, ground noise can cause the ADC readings to fluctuate by ±5 LSB.

• Implementation examples / common mistakes Implementation: use a solid ground plane, but define functional regions within it — AGND under analog components, DGND under the microcontroller and digital logic.

  Connect the two regions at a single point (using a 0 Ω resistor or bridge) beneath the ADC package or at the location recommended by the manufacturer (often the AGND and DGND pins of the IC are tied together internally or at a specific point, forming the star connection).

  No signal traces should cross the split between ground regions except at the bridge point — otherwise, a large loop can form, effectively acting as an antenna.

  Common mistake: using one monolithic ground plane where both high-current FPGA switching currents and low-level sensor return currents share the same path — digital noise couples into the analog section.

  Another mistake: separating the grounds but failing to connect them properly — this can leave parts of the system floating, making it more vulnerable to ESD and interference.

Rule Isolate sensitive analog nodes through physical separation and shielding.

• Explanation (physical basis) The electric field (E-field) from digital signals or power circuits can induce voltage on high-impedance nodes — for example, op-amp inputs, high-value resistors, or reference nodes.

  The solution is physical separation: keep noisy elements (clock generators, data buses, DC/DC converters) away from sensitive circuits (integrators, op-amps, ADC inputs).

  In addition, use shielding where necessary. This may include metal shielding cans over critical sections or a guard ring — a grounded trace surrounding a high-impedance input and following its geometry. The guard ring intercepts surface leakage currents and induced interference, shunting them to ground before they reach the amplifier input.

• Goal and effect Reduce direct coupling of interference into the analog section. Physical separation provides natural field attenuation (~1/r), while a metal shield or grounded “curtain” reflects or absorbs interference.

  As a result, ADC inputs receive a signal with a better signal-to-noise ratio, and the overall circuit radiates less, since critical nodes are shielded.

• When it is especially important In precision amplifiers (for example, measuring microvolt-level signals), oscilloscope front-end circuits, RF receiver stages (such as LNA blocks, which are typically shielded), and medical devices (ECG amplifiers).

  Even in consumer products — for example, high-gain audio circuits — careful layout is required to prevent hum and noise. The PCB is arranged so that the noisy microcontroller is placed at one end, while the microphone preamplifier is located at the other, often with shielding around it.

• Implementation examples / common mistakes Implementation: allocate space on the PCB for EMI shield cans — typically rectangular areas with a grounded perimeter pad. Place the sensitive circuitry under the shield, and route only the necessary signals inside, preferably through filters.

  Pour protective copper around high-impedance inputs — connected either to a buffer output or to the same potential as the input — to prevent leakage currents (a PCB implementation of the guard ring technique).

  Common mistake: placing a 1 GHz PLL device directly next to an ADC input — the digitized signal then shows a 1 GHz spur.

  Another example: leaving a high-impedance sensor input unshielded while a nearby Wi-Fi module transmits — the radiated field is sufficient to induce interference, and the input effectively “picks up” the signal from the air.

Rule Limit the bandwidth of analog circuits to what is strictly necessary.

• Explanation (physical basis) Filtering is one of the most effective EMC techniques.

  Analog inputs often do not require wide bandwidth. For example, a temperature sensor is slow, and an audio signal is limited to about 20 kHz. Interference, however, is usually high-frequency (tens of MHz from a processor, hundreds of MHz from RF sources).

  By adding a simple low-pass filter (RC or LC) at the input of the analog path, the high-frequency components are attenuated. As a result, interference does not reach the sensitive circuitry.

  Filtering also helps prevent re-radiation. For example, placing a filter at the output of a DAC smooths high-frequency switching steps and prevents them from radiating into the environment.

• Goal and effect Improves noise immunity and reduces radiation by limiting the signal bandwidth.

  Physically, this means attenuating differential-mode interference above the required frequency range at inputs and outputs.

  Even if digital noise is coupled into the circuit, it will not pass through the filter. For example, if an ADC samples a sensor at 100 Hz and an RC filter with a cutoff frequency of 1 kHz is added, a 100 MHz noise component can be attenuated by approximately 100 dB.

• When it is especially important Almost always applied at analog measurement inputs: an RC filter is placed before the ADC (anti-aliasing filter), which also serves as an EMC filter.

  For sensors — thermistors, strain gauges — a narrow-band amplifier combined with filtering is used.

  At the output of Class D audio amplifiers, an output filter smooths the PWM waveform.

  If the analog path must be located near digital noise sources, filtering becomes the first line of defense.

• Implementation examples / common mistakes Implementation: choose a cutoff frequency approximately 5–10 times higher than the useful signal bandwidth, but at least 5–10 times lower than the dominant noise frequencies.

  For example, add an RC network: a series resistor (a few kΩ) at the ADC input and a capacitor (e.g., 10 nF) to ground — resulting in a cutoff in the kHz range, effectively attenuating MHz-range noise.

  For stricter requirements, use second-order filters (LC or active filters).

  Common mistake: connecting a sensor directly to the ADC without filtering — high-frequency digital noise can enter the ADC, where it may alias or cause intermodulation artifacts.

  Conversely, a fast DAC output without filtering can also radiate high-frequency components.

Rule Power analog circuits from local regulators or filters, isolating them from noisy supply rails.

• Explanation (physical basis) Even if the grounds are separated, noise can still couple through a shared supply rail (for example, a common 5 V rail powering the entire device). Sensitive analog nodes require a clean supply.

  A typical approach is: main 5 V rail → LC filter or ferrite bead + capacitor → analog 5 V rail.

  Alternatively, use a dedicated low-noise LDO (linear regulator) to filter high-frequency ripple.

  A ferrite bead in the supply path behaves like a resistor at high frequencies (for example, 100 Ω @ 100 MHz), attenuating noise, while an LDO can provide 60–80 dB of rejection at 1 MHz and above.

  This prevents switching noise from propagating into the sensitive analog section.

  
  

• Goal and effect Ensure a low noise level on the supply rails of analog blocks. This directly improves accuracy and reduces radiation (a noisy reference source can itself become a source of interference).

  It also localizes disturbances within functional blocks: for example, if an amplifier starts oscillating at high frequency, the supply filter prevents that noise from spreading across the entire board.
  

• When it is especially important In precision measurement systems (24-bit ADCs, low-level sensors), in audio DACs/ADCs and amplifiers (where even 1 mV of noise is audible), clean power is essential.

  The same applies to RF sections: VCOs and LNAs are typically powered through dedicated filters.

  In mixed analog/digital designs, the digital 3.3 V rail and the analog 3.3 V rail are almost always supplied through separate LC filters or LDO regulators.
  

• Implementation examples / common mistakes Implementation: a common recommendation is: “Place a ferrite bead between VDD and AVDD pins, and add 10 µF + 0.1 µF capacitors at AVDD.” This is a typical arrangement.

  Ferrite bead: 100–200 Ω @ 100 MHz, with sufficient current rating.

  LDO example: take the digital 5 V rail and use an LDO to generate a separate 4.8 V analog rail. At currents of only a few milliamps, this is not an issue, and it removes most of the high-frequency noise.

  Common mistake: directly powering both a noisy microcontroller and a precision ADC from the same supply without filtering. In that case, the data acquisition IC will pick up every switching transient from the digital logic, degrading SNR and potentially coupling that noise back out through its analog ports.

Rule Provide a proper reference ground for sensors and shields.

• Explanation (physical basis) When using remote sensors, cable shields, or chassis grounding, it is important to ground them at a single point in the system to avoid forming loops.

  For example, a shielded microphone cable should have its braid connected to the PCB ground at only one end (typically at the receiver side). Otherwise, currents can circulate in the shield and couple noise into the signal.

  The same applies to sensor housings: connect them to the nearest analog ground, but not at multiple points. This prevents ground loops — situations where two ground paths form a closed loop that can pick up magnetic fields like a coil (for example, 50 Hz mains interference).
  

• Goal and effect Improves immunity to low-frequency (including mains) interference and eliminates unnecessary currents flowing through shields.

  From an EMC perspective, this reduces low-frequency radiation (since ground loops can both receive and emit 50 Hz or impulsive interference), and at higher frequencies it prevents shields from acting as unintended antennas.
  

• When it is especially important In data acquisition systems with remote sensors (industrial sensors, audio microphones, medical equipment), it is important to ensure that shielding does not become a path for interference radiation.

  The same applies to measurement instruments — where one sensor may be referenced to chassis and another to ground. These references must be carefully tied together at a single point; otherwise, equalizing currents can flow between them.

  
  

• Implementation examples / common mistakes Implementation: apply the “star ground” principle to sensors — all shields and return paths should converge at a single point (often a grounding bolt or a defined point on the PCB near the input connector).

  If the system connects to another device, it may be necessary to use a resistor or ferrite in the ground path to limit circulating currents, or to apply galvanic isolation (for example, optocouplers or isolated interfaces).

  Common mistake: connecting cable shields at both the sensor side and the device side. If there is a potential difference between the two grounds, current will flow through the shield, creating interference. In audio systems, this appears as ground-loop hum.

Explanatory notes:

In EMC practice for analog circuits, the key concept is “separate and shield.” Classic literature (for example, Henry Ott) emphasizes that there is no universal grounding recipe for every case — but fundamentally, a solid, uninterrupted ground plane is almost always the best starting point. Functional separation can then be implemented within that plane as needed.

Many modern experts recommend a pragmatic approach: if in doubt, use a single ground plane, place the analog section in one area of the PCB and the digital section in another, and avoid routing signals across sensitive boundaries. This helps prevent common mistakes (such as routing high-frequency signals over ground splits). If necessary, a ferrite bead can later be inserted between AGND and DGND at a defined connection point — at high frequencies the ferrite behaves as impedance, reducing noise coupling, while at DC and low frequencies it keeps the grounds tied together.

The guard ring (or guard trace) technique deserves special attention. For example, around an op-amp input with 10 MΩ impedance, designers often draw a ring connected to the same potential as the input (such as the output of a buffer or a mid-supply reference). This prevents leakage currents through the PCB material (especially in humid conditions) and provides a shielding effect against external electric fields. On a PCB, the guard ring should pass as close as possible to the sensitive input node, surround it fully (360°), and be tied to a stable potential (usually a buffer output). While this is a detail of analog design, it also improves EMC by reducing susceptibility to interference.

Signal edge rates follow similar principles as in digital design: slower transitions are less prone to radiation. For example, in a PWM audio amplifier, the output filter smooths switching edges — otherwise, the speaker wires can act as antennas. ADC inputs do not need to respond to 100 MHz signals; adding a filter both prevents aliasing and reduces high-frequency noise coupling into the board.

Finally, consider common-mode behavior: if the analog ground connects to chassis, this should also be done at a single controlled point. A common practice is to connect the analog ground near the connector to chassis through a 1 MΩ resistor in parallel with a 4.7 nF capacitor — providing DC isolation while offering a low-impedance path for ESD events. This allows static charge to dissipate without creating 50 Hz ground loops.

4. RF Circuits (Transmitters, Receivers, Matching Networks)

Radio-frequency (RF) circuits are a special category where the signals themselves are high-frequency electromagnetic radiation (for example, a 2.4 GHz Wi-Fi transmitter). The goal of the design is to direct that energy where it is intended to go (into the antenna) and prevent leakage where it should not go (into the rest of the circuitry or outside allowed limits).

RF stages are also highly sensitive to noise from digital circuits. Below are rules that support EMC in the context of RF signal paths.

Rule Impedance matching and controlled-impedance RF routing (50 Ω).

• Explanation (physical basis) Any trace leading to an antenna or connecting RF modules must be designed as a transmission line with a defined characteristic impedance (typically 50 Ω for antennas, 50–75 Ω for video, 90–100 Ω differential for balanced interfaces).

  If impedance is not controlled, part of the RF signal will be reflected back into the device, and part may radiate from the trace itself.

  A properly designed 50 Ω microstrip (or stripline) ensures maximum power transfer to the antenna and minimizes standing waves that could otherwise radiate.

  Physically, this means using a specific trace width at a defined distance from a ground plane, and often enclosing it with grounded vias (coplanar waveguide with ground) to better confine the electromagnetic field.

• Goal and effect Achieve efficient RF signal transfer and avoid parasitic radiation or losses.

  A properly matched RF path minimizes unintended radiation (ideally, all energy is delivered to the antenna).

  It also simplifies regulatory compliance: for example, FCC testing evaluates not only the fundamental frequency but also spurious emissions — impedance mismatch can generate additional unwanted emissions at harmonic or other frequencies.

• When it is especially important In all RF designs — from a simple PCB with an ESP8266 Wi-Fi module to complex RF boards for mobile phones.

  If the frequency exceeds 100 MHz and the trace length is more than a few centimeters, controlled impedance cannot be ignored.

  This is especially important for transmitters with significant output power: impedance mismatch leads to power loss and reflected waves, which can radiate unintentionally or even damage the output transistor.

• Implementation examples / common mistakes Implementation: use a defined transmission-line structure — either microstrip (trace on the outer layer over a ground plane) or stripline (trace between two ground planes).

  Calculate the trace width. For example, with FR4, h = 1.0 mm to the reference plane and εr ≈ 4.3, a 50 Ω microstrip may require roughly ~1.8 mm width (verify with an impedance calculator or field solver).

  Account for solder mask — covered copper slightly changes the effective dielectric constant and impedance.

  Add via fencing — a row of grounded vias along the trace, typically spaced on the order of λ/10 to λ/20 (and close enough to confine the field), to contain the electromagnetic field and prevent surface-wave or parallel-plate modes from propagating across the board.

  Common mistake: routing from the RF IC output to the antenna with a thin, uncontrolled trace, or worse, introducing sharp bends and layer transitions without proper impedance control. The result is degraded VSWR, power loss in the PCB, and strong parasitic E-field radiation.

Rule Minimize the length of unshielded RF traces and conductors.

• Explanation (physical basis) An RF signal on an exposed conductor will radiate — effectively acting as an antenna. Therefore, all conductors between oscillators, RF stages, and antennas should be as short as possible, and preferably shielded.

  Shielding may mean using a coaxial cable or connector, or a tightly grounded PCB structure (such as via fencing).

  The longer the trace, the more it can both radiate and pick up interference.

  Ideally, the RF chip is placed as close as possible to the antenna or RF connector. If distance is unavoidable, use coaxial cable or a properly designed waveguide structure.

• Goal and effect Reduction of uncontrolled radiation and losses.

  A shorter RF path means lower attenuation and a reduced chance of acting as an unintended antenna at a resonant frequency.

  From an EMC perspective, the benefit is that the device does not radiate along the trace to the antenna — only the antenna itself radiates, as intended.

• When it is especially important On Wi-Fi/Bluetooth boards, the chip antenna is typically placed within 5–10 mm of the transceiver.

  In higher-power transmitters, a coaxial feed line is often used to connect to the RF connector.

  If RF routing across the PCB is unavoidable (for example, between RF amplifier stages), it is preferably done on an internal layer as a stripline between two ground planes — this minimizes radiation.

• Implementation examples / common mistakes Implementation: follow the principle “RF at the board edge.” Antennas or RF connectors that interface with the outside world should be placed along the PCB perimeter, with the RF transceiver located as close as possible, so the connecting trace is short and direct.

  Between RF stages (amplifier – filter – mixer), keep distances much smaller than λ/4. For frequencies above 1 GHz, designers typically aim for trace lengths under 1 cm.

  Common mistake: placing the antenna deep inside the board and routing it with 5–10 cm of PCB trace. Such a line will inevitably radiate (often at harmonics) and pick up digital noise, degrading spectral performance. Passing out-of-band emission limits then becomes difficult.

Rule Separate the RF section from noisy digital circuitry and use shielding.

• Explanation (physical basis) An RF receiver (and transmitter) is highly sensitive to noise — for example, digital bus activity can couple into the receiver as interference.

  Therefore, the RF section should be physically separated on the PCB (often assigned its own area or quadrant), surrounded by ground and kept away from microprocessors, DC/DC converters, and other noisy circuits.

  Additionally, it is typically covered with a metal shield can, soldered to ground around its perimeter, to prevent external fields from penetrating.

  Inside the shield, components such as the VCO, LNA, and PA are placed close together. Their traces are routed on the top layer, with a solid ground plane directly beneath — effectively forming a controlled enclosure.

  The shield also contains RF emissions within the section, preventing them from coupling into adjacent digital traces.

• Goal and effect Ensure that the RF block operates with the required sensitivity and selectivity, without degradation from digital noise.

  At the same time, prevent the rest of the system from picking up unintended RF emissions from the high-frequency section.

  Overall, this supports compliance with emission regulations. For example, FCC requirements limit spurious emissions at reference clock frequencies, harmonics, and other unintended bands — something that is difficult to achieve in complex devices without proper shielding.

• When it is especially important In cellular modules and Wi-Fi/Bluetooth modules, there are typically two shields: one covering the RF section (everything above ~100 MHz) and another covering the baseband processor.

  In consumer devices such as phones and laptops, shielding is mandatory.

  In simpler designs (for example, single-chip radio modules), the RF section may already be shielded inside the module itself. However, if you are routing discrete RF components on your own PCB, a shield is almost always required.
  

• Implementation examples / common mistakes Implementation: allocate space on the PCB for a soldered shield frame — a perimeter line of pads around the RF section.

  Be sure to place enough ground vias along the perimeter and within the section (approximately every ~3 mm) to connect the top and bottom ground planes — this creates a “Faraday box.”

  From a placement standpoint, isolate the RF section. For example: on the left, the power supply under shield 1; on the right, the microcontroller under shield 2; and at the top edge, far away, the antenna and matching filters under shield 3.

  Common mistake: trying to save cost by leaving the RF section unshielded. The board may work, but it becomes highly unpredictable in the presence of external radiation (a nearby phone can desensitize the receiver), and it may fail regulatory compliance by radiating harmonics.

Rule Provide proper ground (reference plane) for the antenna and matching network.

• Explanation (physical basis) If an antenna is placed on the PCB (monopole, loop, or F-antenna), the way the surrounding ground is implemented is critically important. For example, a monopole antenna requires a counterpoise — a sufficiently large ground plane beneath and around it. Without this, it will not tune properly and may begin to pick up power supply noise.

  For a patch antenna, the situation is the opposite: it requires a continuous ground plane beneath it at a specific distance, forming a resonant cavity.

  The general principle is to follow the antenna manufacturer’s recommendations or verified design calculations — specifically regarding where ground cutouts must be made and what dimensions the ground area should have.

  In addition, the matching network (typically composed of L-C components placed between the RF chip and the antenna) must be positioned as close to the antenna as possible. These components themselves should be located adjacent to a solid ground plane, ensuring that every capacitor or inductor connected to ground has a short and direct path to the ground polygon.

  All nodes where high-frequency current returns to ground must use multiple vias to minimize inductance.

• Goal and effect If an antenna is placed on the PCB (monopole, loop, or F-antenna), the way the surrounding ground is implemented is critically important. For example, a monopole antenna requires a counterpoise — a sufficiently large ground plane beneath and around it. Without this, it will not tune properly and may begin to pick up power supply noise.

  For a patch antenna, the situation is the opposite: it requires a continuous ground plane beneath it at a specific distance, forming a resonant cavity.

  The general principle is to follow the antenna manufacturer’s recommendations or verified design calculations — specifically regarding where ground cutouts must be made and what dimensions the ground area should have.

  In addition, the matching network (typically composed of L-C components placed between the RF chip and the antenna) must be positioned as close to the antenna as possible. These components themselves should be located adjacent to a solid ground plane, ensuring that every capacitor or inductor connected to ground has a short and direct path to the ground polygon.

  All nodes where high-frequency current returns to ground must use multiple vias to minimize inductance.

• When it is especially important In all devices with integrated antennas—Wi-Fi dongles, Zigbee devices, GPS modules—achieving the specified range and sensitivity requires careful implementation of the ground area. In an EMC context, poor grounding can lead to out-of-band emissions or unstable oscillation, which may violate, for example, regulatory requirements for the spectral mask.

  Implementation
  

• Implementation examples / common mistakes Implementation:For example, for a quarter-wave PCB antenna at 2.4 GHz, stitch the adjacent edges of the board to ground with a dense via fence, and do not place any ground copper directly beneath the antenna for a distance of approximately 5 mm (this allows it to “breathe”). At the same time, make sure that the power distribution network does not run through this area—otherwise it will become part of the antenna system.

  Matching:Place the L and C components between the chip’s RF output and the antenna as tightly as the package and layout constraints allow, and add 3–4 ground vias next to each capacitor to provide a low-inductance return path.

  Typical mistakes:Installing a monopole antenna in the middle of the PCB above a solid ground plane—then it simply will not operate as a monopole (it requires an edge placement and a counterpoise). Or the opposite extreme: the antenna radiates well, but there is a nearby power copper pour that is not tied to ground—this pour can start resonating and will degrade the radiation pattern and/or impedance.

Rule Power-supply filtering and shielding of auxiliary RF circuits.

• Explanation (physical basis) Inside an RF block, there is not only the RF signal itself, but also elements such as the reference oscillator (XTAL), the data interface to the microcontroller (e.g., SPI), and control lines. These signals can both generate interference and be susceptible to it.

  All lines entering a shielded enclosure must be properly filtered. The power supply should pass through a π-filter (ferrite bead plus capacitors). Digital control lines should be conditioned at least with a series resistor or an RC network to suppress fast edges before they enter the RF section.

  In some designs, specialized filtered connectors or feedthrough capacitors are used to route signals into a shielded module; these components block high-frequency leakage. It is also common practice to place an LDO regulator inside the RF section to isolate its supply from the rest of the board. Combined with an LC filter, this provides a clean voltage rail.

  Another critical function of the shield is to prevent radiation from the reference oscillator. A 40 MHz crystal, for example, can radiate noticeably on its own, so it is typically kept inside the shield, and both its supply and signal paths are filtered accordingly.

• Goal and effect The objective is to reduce the penetration of digital noise into the RF section and prevent RF signal leakage to the outside.

  An unfiltered power supply can allow noise from digital logic to couple into the transmitter, modulating the carrier signal (digital activity may appear in the spectrum as spurious emissions). In a receiver, supply noise can raise the noise floor, degrading sensitivity.

  Filtering on control lines prevents high-frequency components—such as the fast edge of an SPI CS signal—from propagating along conductors as unintended antennas beneath the shield. Even narrow gaps can radiate if not properly controlled.

• When it is especially important In radio modules (Wi-Fi, LTE), an EMI filter is always placed at the power input, often implemented in multiple stages in order to meet stringent power-supply noise requirements (for example, −80 dB limits).

  If your product consists of a microcontroller with an external radio module, ensure that the control signals are within acceptable limits—excessively high switching frequency or fast transitions on these lines can interfere with the radio’s operation.

• Implementation examples / common mistakes Implementation: Place ferrite beads on the VCC_RF supply line (1000 Ω @ 100 MHz), followed by a 10 µF tantalum capacitor and 0.1 µF / 0.01 µF ceramic capacitors positioned close to the chip.

  Use a local LDO regulator: for example, derive 3.0 V for the RF section from the main 3.3 V rail via an LDO with a PSRR of 60 dB at 1 MHz.

  For control lines, add 51 Ω series resistors on MOSI, MISO, and CS near the point where the signals enter the shielded area, forming an RC filter together with the input capacitance.

  Place the crystal as close as possible to the chip, surround it with a ground “moat,” and keep the grounding capacitors connected with the smallest possible loop area.

  Common mistakes: Routing unfiltered lines directly into the RF enclosure is equivalent to cutting slots in the shield. These lines can carry RF energy out or bring noise in. Likewise, leaving a long, unfiltered power trace feeding the RF section effectively invites noise into the system.

Explanation: Designing PCBs with RF circuitry is an extensive discipline and directly tied to EMC considerations. At frequencies in the hundreds of MHz and into the GHz range, even traces a few centimeters long begin to behave as antennas. The fundamental rule is straightforward: the higher the frequency, the smaller the physical structures that can effectively radiate.

For example, a 5 mm slot in a shield can begin to radiate at approximately 30 GHz (λ/2 ≈ 5 mm), which is not critical for most consumer-frequency applications. However, a 1 mm opening becomes efficient at around 150 GHz. As a result, seemingly minor details—such as a missing shield screw or an unfilled via—can become leakage paths for high-frequency energy.

From a regulatory standpoint, organizations such as Federal Communications Commission (FCC) and European Telecommunications Standards Institute (ETSI) require radio transmitters to limit emissions outside their designated operating bands. Without proper design, a PCB may radiate transmitter harmonics (for example, the second harmonic) or allow digital noise to couple into the antenna. The techniques discussed—filtering, shielding, and impedance matching—are intended to prevent precisely these issues.

In receivers, the primary risk is sensitivity degradation due to noise and intermodulation interference. Intermodulation can occur, for instance, when a digital clock frequency (e.g., 48 MHz) mixes with a local oscillator signal (e.g., 1000 MHz), producing a spurious tone within the receive band (1000 − 48 = 952 MHz; if this falls within the channel, the receiver becomes effectively desensitized). Such effects are typically revealed during compliance testing under standards such as CISPR 25 or MIL-STD-461 for sensitive equipment.

The mitigation approach is comprehensive shielding of all signal-generating circuitry and filtering of every line entering or leaving the RF section. For example, in automotive AM/FM receivers, the PCB is physically partitioned: the digital section (processor, memory) is enclosed with shields and filters, while the analog RF tuner section is isolated separately. The two domains are then interconnected using optical isolation or differential signaling to minimize interference coupling.

5. Microcontrollers, SoCs, and especially FPGAs with multiple power/ground pins

Large digital ICs (MCUs, processors, FPGAs) are characterized by a high density of switching activity—dozens to hundreds of pins may change logic state simultaneously. This results in supply current transients and ground bounce, which can generate EMI and disrupt proper operation.

In addition, such devices are typically connected to high-speed interfaces and therefore require a carefully designed power distribution network (PDN – Power Distribution Network).

Rule Use multilayer PCBs with dedicated power and ground planes.

• Explanation (physical basis) Large BGA packages with hundreds of pins are practically impossible to route on two layers without significant EMC compromises. Dedicated internal planes for solid ground and power provide several critical advantages:

  1. Low return-path inductance for all signals, which is essential for reducing radiation and minimizing ground bounce.

  2. Built-in interplane capacitance for high-frequency decoupling—each VCC–GND layer pair forms a distributed capacitor with low ESR.

  3. Shielding of internal signals by adjacent ground planes—return currents close between layers rather than radiating outward.

  Without this structure—for example, on a two-layer board—long microcontroller buses will form large current loops, with return paths forced through power traces. This increases noise, loop area, and radiated emissions.

• Goal and effect Provide an electrically “quiet” reference for the device and reduce radiation from its signal buses. This is especially important for minimizing the effects of Simultaneous Switching Noise (SSN): when many pins switch at once, they disturb the local ground and power rails. This can both generate radiation (with planes behaving like antennas) and lead to functional errors.

  A multilayer structure mitigates this issue by providing low-impedance current return paths.

• When it is especially important For FPGAs with dozens of I/Os switching simultaneously, for high-speed microprocessors (100+ MHz), and for any designs with wide parallel buses (for example, a 32-bit address/data bus), a multilayer PCB is strongly recommended.

  As a practical guideline, if a digital IC has more than 50 pins, it is advisable to plan for at least a four-layer board.

  Regulatory standards such as CISPR 32 and Federal Communications Commission (FCC) requirements effectively mandate this for high-speed devices. A two-layer board will typically fail to meet Class B emission limits above 100 MHz due to radiation from signal routing.

• Implementation examples / common mistakes Implementation:

  A typical stack-up:Signal – Ground – Power – Signal.

  Alternatively:Ground – Signal – Power – Ground, which provides better shielding but is more difficult to route.

  All VCC pins of the chip should be connected with short vias directly into the Power plane, and all GND pins into the Ground plane directly beneath the device.

  In this configuration, a local interplane capacitance is formed inside the BGA area between the Power and Ground planes. If they are separated by a thin dielectric (e.g., 0.1 mm), several nanofarads of capacitance can be achieved directly “under the chip.”

  Common mistake:Placing an FPGA on a two-layer board, with power supplied through narrow traces and ground implemented as a grid. During switching events, the supply voltage fluctuates, interfaces become unstable, and harmonic radiation of the clock frequency is emitted due to antenna effects in the routing.

Rule Place decoupling capacitors of various values generously around the package.

• Explanation (physical basis) Large ICs draw pulsed current with extremely fast edges (rise times <1 ns, with current steps of milliamps or more). No single capacitor remains effective across the entire frequency spectrum.

  For this reason, a multi-capacitor decoupling strategy is used:

  • 0.01 µF (or 4.7 nF) for the highest frequencies (self-resonance typically in the hundreds of MHz),

  • 0.1 µF for the tens of MHz range,

  • 1–10 µF for the lower MHz range,

  • and larger 10–100 µF tantalum capacitors for the tens of kHz range.

  These capacitors are placed around all sides of the package—or even beneath it in the case of a BGA—so that the distance from each power pin to its decoupling capacitor is minimized (typically <5 mm).

  Physically, multiple capacitors connected in parallel reduce the PDN impedance across a wide frequency band. This prevents resonant impedance peaks that could otherwise cause local voltage droop and large transient currents, which in turn generate radiated electromagnetic noise.

• Goal and effect Providing stable local power for the IC and minimizing noise currents in the planes. The more high-frequency capacitance available close to the chip, the less the current “wanders” across the board in search of supply energy (that is, large current loops carrying noise are avoided).

  This reduces both radiated emissions and susceptibility to external interference (power-supply immunity).

• When it is especially important All FPGA and CPU design guides specify the required number of decoupling capacitors. For example, Xilinx recommends approximately one capacitor per pair of FPGA power pins.

  In high-speed DACs and ADCs, multiple ceramic capacitors are often placed directly beneath the package.

  Without sufficient decoupling, much of the EMC effort becomes ineffective: the board will radiate at the resonance frequency of the power distribution network (typically in the tens of MHz range).

  
  

• Implementation examples / common mistakes Implementation: Place 0.1 µF capacitors (X7R, 50 V, 0402) evenly around the perimeter of the IC, each located no more than 3–5 mm from its corresponding VCC pins. In addition, position several higher-value capacitors (1–4.7 µF, 0805) along the diagonals of the package.

  For BGA devices, small 0201 capacitors can be mounted on the opposite side of the PCB directly beneath the chip, connected through vias to the appropriate power pins (this approach is commonly used for FPGA core supplies).

  Use multiple vias to both GND and VCC pads of each capacitor to reduce connection ESL.

  Common mistakes: Attempting to save on capacitors by placing only a few 0.1 µF units for the entire chip. This leads to impedance peaks; for example, all power pins become coupled through plane inductance, and around ~100 MHz a supply droop may occur, resulting in noise and radiation.

  Another frequent mistake is placing capacitors too far away (1–2 cm). At high frequencies, their effectiveness is nearly zero—they cannot respond quickly enough to supply fast transient currents.

Rule Optimize the connection of capacitors to the planes (minimize connection inductance).

• Explanation (physical basis) Even a large number of capacitors will not help if they are connected with long, narrow traces. The inductance of 1 mm of trace is on the order of 1 nH; if the current changes at 1 A/ns, this results in a 1 V voltage drop across that parasitic inductance alone.

  For this reason, it is critical to place vias directly at the capacitor pads—preferably 2–4 vias per terminal.

  It is recommended to place one via for +VCC and one via for GND as close as possible to the corresponding capacitor pads (or directly in them). The shorter the path, the lower the ESL and ESR, and the closer the capacitor behaves to an ideal component at high frequencies.

  Whenever possible, mount the capacitors on the same side as the IC to avoid additional vias.

• Goal and effect Ensure that the actual PDN impedance curve remains low and free of peaks across the required frequency range.

  By minimizing connection inductance, the true performance of SMD capacitors is preserved (a high-quality 0402 capacitor may have an ESL of ~400 pH, but adding 1 nH of trace inductance largely negates that advantage).

  From an EMC standpoint, low connection inductance means that noise currents do not propagate across the board; instead, they close locally through nearby capacitors. This reduces both radiated emissions and unwanted coupling.

• When it is especially important In general, this is always important, but it becomes especially critical for large BGA devices with core supplies operating at hundreds of MHz. It is also essential in circuits with fast current transients—such as processor VRMs (Voltage Regulator Modules) and memory drivers. In such cases, embedded capacitors integrated into the PCB stack-up are sometimes used.

• Implementation examples / common mistakes Implementation: During layout, ensure that the pads of each decoupling capacitor are connected to the power and ground planes through multiple short vias. Many CAD tools provide a “via stitching” function—use it to place at least two vias on the GND pad of each 0402 capacitor.

  Larger bulk capacitors (10–47 µF) should also be equipped with multiple vias—typically four per capacitor. Although they primarily support lower frequencies, minimizing their connection inductance remains beneficial.

  Common mistake: Connecting a 0.1 µF capacitor to the IC power pin through a thin trace. This can add 5–10 nH of inductance, effectively turning the capacitor into a resonant element rather than a decoupling component.

  A frequent layout error is a capacitor placed near the device, but connected via a long, narrow trace to a distant power via. At frequencies above ~50 MHz, this provides little to no decoupling effect and may even introduce an additional resonance.

Rule Account for I/O current balance and use “blind” (dedicated internal) layers for noisy nets.

• Explanation (physical basis) When many I/O lines switch simultaneously, SSN (Simultaneous Switching Noise) occurs due to the summation of return currents in the power and ground networks.

  One approach is at the system level—avoid switching all lines at once (for example, introduce small delays). At the PCB level, the following measures can be taken:

  1. Distribute critical lines across different layers and surround them with ground to reduce coupling.

  2. Route very noisy signals (clock sources, fast edge signals) on internal layers between two ground planes whenever possible. This confines their electromagnetic field within the PCB structure and reduces radiation.

  In addition, disable unused interface pins and avoid leaving them floating. Tie them to a defined logic level (pull-up or pull-down), since unused floating pins can pick up interference and generate parasitic currents.

• Goal and effect Reduce overall system noise from simultaneous switching and minimize radiation from the most “active” signals.

  Internal layers behave like waveguides: the signal propagates between two ground planes, and its external electromagnetic field is significantly confined. In contrast, signals routed on outer layers allow the field to extend into free space.

  Therefore, routing a CPU clock line, for example, on an internal layer can substantially reduce its radiation—similar in concept to a coaxial structure without a full enclosure, but still achieving approximately 70–80% field containment.

• When it is especially important On high-density FPGA boards (8–12 layers), critical signals—such as differential clocks and memory data lines—are typically routed on internal layers.

  On a four-layer PCB, this is more constrained, but it is still possible to assign selected critical nets to an internal layer while reserving the top layer for less noisy signals.

• Implementation examples / common mistakes Implementation: Use pin configurations that reduce the likelihood of all bits switching simultaneously. For example, in an FPGA, adjust drive strength and slew rate settings—select the minimum values that still meet signal integrity requirements (slower edges produce a narrower spectral content).

  During routing, place critical signals on an internal layer—for example, route them on layer 3 between ground planes on layers 2 and 4. This cavity-like structure confines their radiation within the PCB.

  Common mistakes: Routing a primary 200 MHz clock signal across the entire board on the top layer—this effectively turns it into an antenna.

  Failing to connect the FPGA’s exposed pad or shielding pins to ground, which compromises the device’s internal shielding.

  Leaving long unterminated stubs on FPGA outputs (for example, test or debug traces). Such stubs can radiate strongly due to reflections and resonance.

Rule Apply proper grounding topologies for connectors and mounting points.

• Explanation (physical basis) PCBs with large MCUs or FPGAs are often connected to other boards or to the enclosure through connectors or mounting screws. An important EMC rule is that all such connections must have a solid ground reference to avoid forming unintended antennas.

  For example, if a ribbon cable connector carries high-speed signals, adjacent ground contacts should be provided (e.g., every second pin as ground, or a shielded housing).

  Mounting holes: if a chassis ground is defined, these pads should be connected to the internal ground through the mounting screw (optionally via an RC network to control current flow). This establishes a reference shield for the entire board.

  If a connector is left without a proper ground reference, each signal line effectively extends “into free space,” increasing both radiation and susceptibility to interference.

• Goal and effect Minimize radiation at interconnect points and protect against external interference conducted through cables.

  A proper chassis connection also provides a discharge path for ESD events, directing the energy through the enclosure rather than allowing it to arc across the PCB.

  If the board is enclosed in a shielded housing, a low-impedance connection between the PCB ground and the chassis ground must be ensured. Otherwise, the enclosure will not function effectively as a shield.

• When it is especially important In all equipment required to comply with IEC 61000-4-2 (ESD) and IEC 61000-4-6—that is, virtually all commercial and industrial devices where the enclosure may be exposed—proper grounding and chassis bonding are essential.

  For regulatory compliance such as Federal Communications Commission (FCC) requirements, providing a ground connection at cable connectors (for example, VGA and HDMI connectors with grounded metal shells) helps reduce emissions.

• Implementation examples / common mistakes Implementation: For example, in a 40-pin ribbon connector to another board, allocate approximately 10 pins as GND. Distribute them evenly—e.g., one ground pin after every 3–4 signal pins—and connect them directly to the ground plane.

  For a USB connector, solder the metal shell to the PCB and connect it to ground (often through an ESD network such as 1 MΩ in parallel with 4.7 nF).

  For mounting hardware, use a serrated washer under the screw to break through oxide layers and ensure reliable electrical contact between the metal enclosure and the PCB ground planes.

  Common mistakes: Leaving mounting holes floating and not connected to ground. In this case, the enclosure and the PCB can behave as two coupled resonant structures. During radiated immunity testing (e.g., IEC 61000-4-3), RF voltage may be induced between them, causing malfunction.

  Another issue is a floating metal connector shell. During an ESD event, charge accumulates on the shell and then discharges through unintended paths into the circuitry, leading to system disturbances or failure.

Explanation:

This category brings together a number of general principles that are critical for system-level EMC.

With a large number of nets and components on a PCB, the overall power distribution network (PDN) impedance becomes a dominant factor. A modern design approach is to calculate the Target Impedance of the PDN based on the allowable voltage ripple (ΔV) and the maximum current transient (dI). For example, if an FPGA draws a 10 A transient and the allowable droop is limited to 50 mV, then the required impedance is:

Z = 50 mV / 10 A = 5 mΩ

at the relevant switching frequencies.

Achieving this requires a combination of distributed capacitance and solid power/ground planes. Typical design targets are:

• PDN impedance < 50 mΩ up to the hundreds of kHz range

• PDN impedance < 0.5 Ω up to the hundreds of MHz range

Failure to meet these targets not only risks functional instability but also increases emissions. When impedance is high at a particular frequency, the power and ground structures can resonate and “ring,” radiating like a large loop antenna.

Ground bounce is the phenomenon where multiple IC outputs switch simultaneously and, through the inductance of package leads and PCB traces, shift the chip’s local ground potential relative to the board. This can cause logic errors (due to reduced noise margins) and increased radiation (as the entire IC effectively behaves like a dipole relative to the PCB ground). Mitigation measures include multilayer stack-ups, extensive decoupling, and controlled edge rates.

Additional system-level techniques include staggered switching—for example, introducing slight delays so that not all 8 data bits switch at the exact same instant. This approach is sometimes used in memory systems. Encoding methods such as Gray code can also reduce simultaneous transitions (avoiding cases like 255 → 0 where all bits toggle). While these techniques extend beyond PCB layout, they contribute significantly to EMC performance.

Enclosure shielding:If the device is housed in a metal enclosure, the PCB should be bonded to it so that the enclosure acts as a Faraday cage. Contact springs or screw pads are often placed around the PCB perimeter to ensure reliable electrical connection.

However, large ground currents should not be routed through the enclosure, as this can turn it into an unintended radiator. Therefore, at the power entry point, the enclosure is often connected to the PCB ground through an EMI network (for example, Y-capacitors on mains input, or RC networks on signal lines).

A properly grounded enclosure provides a substantial EMC advantage: radiated emission levels are significantly reduced because energy is confined inside the housing. Improper grounding, however, can create ESD problems—for example, discharges from the enclosure into the PCB.

6. Protection against ESD and external interference

Electrostatic discharges (ESD) and external electromagnetic воздействия (EMP, RF fields) are part of a device’s immunity testing. To comply with standards such as IEC 61000-4-2 (ESD), 61000-4-4 (EFT—electrical fast transients), 61000-4-5 (surge), and others, the PCB must not be damaged and must not malfunction.

The PCB designer must provide defined discharge paths for such disturbances and protection for all inputs and outputs.

Rule Provide “ESD receivers”—TVS diodes and discharge elements at connectors, with the shortest possible path to ground.

• Explanation (physical basis) When a discharge strikes an exposed connector or cable (for example, 8 kV per IEC 61000-4-2), the current seeks a path to ground. A short, low-inductance return path must be provided. Otherwise, the discharge current will propagate across the PCB, potentially damaging components and generating radiated interference.

  A TVS diode (Transient Voltage Suppressor) is designed to avalanche rapidly under overvoltage conditions, diverting the surge current to ground. It must be placed as close as possible to the discharge entry point (the connector) and connected to a large ground or chassis plane through a dedicated via located adjacent to the device.

  Spark gaps and gas discharge tubes are also used for the same purpose—to intercept the surge at the point of entry.

  In addition, PCB pads and copper shapes should avoid sharp corners, as these concentrate electric fields and increase the likelihood of unintended breakdown.

• Goal and effect Protect sensitive electronics from high-voltage transients and minimize RF emissions caused by ESD events.

  If the discharge is intercepted and diverted through dedicated protection devices, it does not penetrate deeply into the circuitry. As a result, it does not disturb logic operation and does not radiate through PCB structures acting as unintended antennas.

  A short, low-impedance path to ground ensures that most of the discharge current flows into the board’s ground system rather than into the surrounding air—which would effectively act as a radiating source.

• When it is especially important

  For any user-accessible interface—USB, HDMI, push buttons, external ribbon cables, antenna connectors—ESD protection is required. Even if not explicitly mandated, including TVS devices is an inexpensive form of insurance.

  This is particularly critical in medical, aerospace, and automotive applications, where ESD testing may simulate discharges up to 15–25 kV.

• Implementation examples / common mistakes

  Examples:

  For a USB port, a TVS array is placed on the D+ and D− lines to ground.

  For HDMI, a multi-line TVS array protects all 19 contacts.

  For an automotive power input, a high-power TVS device (e.g., in an SM8S package) is used to withstand surge pulses up to 2 kA, such as those defined in ISO 7637-2 pulse 5a (load dump, comparable in effect to a lightning surge).

  Proper implementation:Place the TVS device within approximately 1 mm of the connector. Connect its ground terminal to the ground plane using at least two vias directly from the GND pad to the polygon.

  Common mistake: Placing the TVS diode deep inside the PCB, with a 5 cm trace between the connector and the protection device. Before the surge current reaches the TVS, it will already have spread across the board, potentially damaging thin traces or sensitive ICs.

Rule Minimize the inductance of the discharge path (wide copper pours, multilayer ground planes)

• Explanation (physical basis) During an ESD event, the current rise rate can reach approximately 1 A/ns, with pulse durations of only a few nanoseconds. An inductance of just 10 nH will produce a voltage spike according to L·di/dt:

  10 nH × 1 A/ns = 10 V,

  which is already comparable to typical voltage tolerances.

  For this reason, any traces carrying ESD current must be as short and as wide as possible. A solid ground plane is preferred, since its impedance is significantly lower than that of a narrow conductor and it distributes the current over a wide area.

  It is also good practice to use two parallel ground layers interconnected with multiple vias, which effectively reduces inductance.

  Where appropriate, a dedicated metal pad or copper area can be added at the entry point, designed to receive the discharge directly and then conduct it safely to the chassis.

• Goal and effect Reduce internal overvoltage and potential differences during a discharge event. Otherwise, an ESD pulse can raise the local ground of a connector to kilovolt levels relative to other parts of the circuit, potentially causing breakdown of internal junctions.

  Low inductance in the discharge path enables rapid diversion of charge into the ground capacitance.

  From an EMC perspective, minimizing inductance reduces the radiated electric field component, since radiated emission is proportional to di/dt and the associated loop inductance.

• When it is especially important In designs where the ESD strike is expected to hit the enclosure or shielding, spring contacts or grounding clips are often used to bond the enclosure to the PCB ground. These distribute the discharge current across the board and prevent internal arcing.

  For connectors, any pin that may be exposed to ESD should ideally have a nearby ground pin. This creates a localized discharge path, similar to a lightning rod placed adjacent to the point of strike.

• Implementation examples / common mistakes Implementation:

  Flood the area near the expected strike point with copper and stitch it generously with vias to the internal ground layers.

  Provide dedicated ground vias specifically for ESD current, so that the discharge does not flow through narrow signal vias.

  In multilayer designs, ensure that ground polygons are present on all layers beneath the connector. This allows the discharge current to distribute in parallel across multiple planes.

  Common mistake:Creating narrow “ground tunnels” to the connector—often due to layout cutouts intended to separate grounds, without considering the ESD discharge path. As a result, a strike at the connector has no direct path to ground and breaks down through unintended parts of the circuit.

Rule Avoid sharp corners, sharp leads, and unconnected “antenna” stubs.

• Explanation (physical basis) Areas with sharp metal protrusions concentrate electric fields. During an ESD event, such points can become sites of localized discharge (corona) or increase radiated emission. For example, a 90° trace corner can experience a higher electric field concentration during a discharge (on the order of several kV/cm), sufficient to ionize air.

  Therefore, sharp corners in copper pours and traces should be avoided; use rounded shapes or 45° angles instead.

  Long, unused conductors (stubs, unused test pins) can also act as antennas. An ESD pulse may couple onto them and be re-injected into the circuit. It is preferable to remove such conductors or connect them to ground through a resistor.

• Goal and effect Prevention of unintended discharge paths and reduction of breakdown risk. Rounding copper corners distributes the electric field more uniformly, so that a discharge is more likely to occur through the intended TVS device rather than at a sharp trace corner.

  Emission reduction: smooth trace geometry radiates less high-frequency energy during fast transients. In some cases, the difference can reach on the order of 5–10 dB compared to sharp-edged layouts.

• When it is especially important This requirement is particularly important for interfaces exposed to high ESD levels (USB, HDMI). Many vendor guidelines—for example, those from Texas Instruments—recommend avoiding 90° bends on such signal lines.

  Clock lines and GPIO traces routed to external buttons should also use 45° routing instead of sharp right angles.

  Unconnected trace ends (leftover stubs from layout revisions) must be removed or properly terminated.

• Implementation examples / common mistakes Implementation:

  During layout, use rounded trace corners (arcs or two 45° bends instead of a single 90° angle).

  Bond metallic structural parts (heatsinks, shields) to ground. If left floating, they can accumulate charge and become discharge sources.

  Minimize exposed, protruding copper features wherever possible.

  Common mistake: Prototype boards with sharp polygon “teeth.” Each sharp corner acts like a needle, concentrating the electric field and potentially initiating breakdown. There have been cases where ESD discharges burned through the PCB substrate precisely at sharp pad corners. This effect should not be underestimated.

Rule Include EMC filters (LC or RC) at inputs to suppress EFT and RF interference.

• Explanation (physical basis) In addition to ESD, external disturbances can enter through cables in the form of fast transients (EFT/Burst—multiple 5 ns pulses, as defined in IEC 61000-4-4) or induced RF currents (IEC 61000-4-6, 0.15–80 MHz).

  To prevent the device from reacting to such disturbances, these signals must be filtered at the entry point.

  EMC suppression filters are used for this purpose. For example:

  • On power lines: a small inductor combined with a capacitor to ground (π-filter) attenuates fast pulses and high-frequency noise.

  • On signal lines: an RC network or a ferrite bead can be used.

  Capacitors must be selected so that they do not degrade the intended signal while effectively shunting high-frequency components (typically 1–10 nF on digital inputs, attenuating frequencies above ~1 MHz).

  Ferrite beads and inductors present high impedance at high frequencies and block conducted interference.

  A common-mode choke on the power cable is also essential, as in standard input filters (e.g., toroidal cores around supply conductors). It suppresses common-mode currents and prevents them from propagating along the cable.

• Goal and effect Improve immunity to external coupling and interference.

  Filters attenuate disturbance energy before it reaches sensitive circuit nodes. As a result, even a strong interference event may only cause a minor signal deviation (for example, a 0.1 V perturbation instead of a 5 V spike).

  These filters operate bidirectionally: they also prevent internally generated noise from propagating onto cables, thereby improving radiated and conducted EMC performance.

• When it is especially important All products seeking CE compliance (EN 61000-4-x series) or automotive qualification (e.g., ISO 7637) must meet immunity requirements.

  For example, if an external power supply produces a 2 kV EFT surge (per IEC 61000-4-4), the PCB must withstand it without resetting.

  Without proper filtering, these pulses couple onto the 5 V rail and disturb the microprocessor.

• Implementation examples Power input connector: an input LC filter is implemented — a series inductor of several tens of µH, followed by 0.1 µF capacitors to ground.

Rule Separate the “power ground” and the “noisy ground” at the power entry point, connecting them through a filter.

• Explanation (physical basis)

  The power input connector from an external source (adapter, battery) is often the primary entry point for conducted disturbances. To prevent these from propagating into the internal ground system, two ground domains can be defined: PGND (chassis, connector, external ground) and GND (internal circuit ground).

  These grounds are interconnected through a filtering bridge—typically consisting of resistors and/or inductive elements in combination with a capacitor. In this arrangement, an external transient is attenuated across the resistive or inductive element and shunted by the capacitor back to the external ground, rather than penetrating the internal circuitry.

  At low frequencies (DC), the potential difference remains negligible—the grounds are effectively connected.

  This approach is also applicable to enclosures: chassis ground is often linked to signal ground through an RC network or a controlled element, allowing static charges and high-frequency components to be diverted while limiting undesired current flow.

  
  

• Goal and effect Improved noise immunity and reduced interference: by isolating the “dirty” domain, the internal circuitry is protected.

  In the event of an ESD strike to the enclosure, the primary discharge current flows into PGND and then through the RC network to the chassis, bypassing sensitive electronic components.

  
  

• When it is especially important For example, in laptops the power connector ground is bonded directly to the chassis, while the system ground is connected through a small 0 Ω resistor or an inductor. This arrangement limits high-frequency noise from the external power supply from coupling directly into the main PCB.

  In automotive systems, the “body ground” (vehicle chassis) and the local electronic ground are often separated at high frequencies to prevent conducted noise from propagating into sensitive circuits.

  
  

• Implementation examples / common mistakes Implementation:

  At the power connector, place a component designated as “BEAD” between the connector ground and the main ground polygon, as well as between the negative terminal and the chassis ground.

  Optionally, add a 4.7 nF capacitor in parallel to provide immediate high-frequency shunting of transient spikes.

  Common mistake: Using a single, uninterrupted ground connection without any damping or filtering element. In the event of an external surge (for example, a lightning-induced transient on the cable), the entire disturbance is coupled directly onto the PCB, potentially damaging control logic or a radio module.

Explanation:

When designing protection circuitry, it is essential to reference applicable standards. For example, IEC 61000-4-2 requires that a device withstand 8 kV contact discharge and 15 kV air discharge without damage or malfunction.

As discussed above, compliance is achieved through a combination of measures: TVS protection devices, separation of ground domains, rounded copper geometry, and proper bonding of enclosures to ground.

For IEC 61000-4-4 (EFT—bursts of fast 5/50 ns pulses) and IEC 61000-4-5 (Surge—longer 1.2/50 µs impulses), protection is primarily provided by input filtering and surge arresters (varistors, gas discharge tubes).

On the PCB, adequate isolation distances must also be considered. For example, a 4 kV surge may require approximately 5–8 mm clearance between primary and secondary sides in a power supply design.

Although this is not directly an EMI issue, it is critical for safety and overall immunity performance.

Cable handling: Cables behave like antennas and are vulnerable to RF currents induced onto them (for example, IEC 61000-4-6 specifies a 3 V sine disturbance up to 80 MHz).

To meet these requirements, a common-mode choke is placed on the cable (as described in the digital-interface section). On power cables, it is also common to add a ferrite sleeve or clamp-on ferrite at the cable end—these are the “beads” often seen on monitor cables.

On the PCB, it is good practice to reserve footprint space for filtered connectors, or to use connectors with integrated filtering (for example, RJ45 jacks with built-in EMI suppression).

A key point is the device’s grounding scheme. If the product is connected to protective earth (for example, a stationary PC with an earthed power supply), then all discharge currents should be directed to that earth reference. If the device is portable (floating ground), the enclosure can be used as the shielding reference instead.

In both cases, IEC 61000-4-3 (radiated RF immunity at 3 V/m) verifies that the device does not malfunction when exposed to a strong external electromagnetic field. The countermeasures are shielding, filtering, and proper grounding/topology, as described above.

7. Standards and regulations (CISPR 25, IEC 61000, FCC, etc.)

Why is all of this necessary? To ensure the product complies with EMC standards that define allowable emission levels and required immunity performance. Brief overview:

• CISPR 25 (Automotive equipment) is an international EMC standard for components used in vehicles. The latest edition, CISPR 25:2021 Ed. 5.0, covers frequencies from 150 kHz to 5.925 GHz. It defines limit levels for radiated emissions (measured with an antenna at a distance of 1 m) and conducted emissions (through the vehicle power network, measured via a LISN).

  It specifies Classes 1 through 5, where Class 5 is the most stringent (intended for equipment located close to antennas, for example in radio receivers). The key implication for us is that meeting Class 5 requires extremely low noise levels—often impossible without shielding and dedicated filtering.

  Automotive EMC requirements also reference ISO 11452 (immunity) and ISO 7637 (transients on supply lines). From a PCB perspective, this translates into: minimal ripple from DC/DC converters, and no noise in the AM bands (0.15–30 MHz), otherwise the in-vehicle receiver will be desensitized or jammed. This is why many of the rules above (small current loops, shielding, filtering) map directly to CISPR 25 requirements. For example, in order not to exceed 20 dBµV at 2 MHz (a very low level), manufacturers recommend techniques such as spread-spectrum control, LC filtering on the power input, and so on.
  

• FCC Part 15 / EN 55032 / IEC 61000-6-… (residential/industrial environments) focus primarily on limiting radiated and conducted emissions that may disturb nearby equipment.

  Under FCC Part 15 (USA), devices are classified as:

  • Class A (industrial/commercial),

  • Class B (residential, stricter limits).

  For Class B, radiated emissions in the 30–1000 MHz range must not exceed specified field strength limits (measured at 3 m distance), for example:

  • 100 µV/m in the 30–88 MHz range,

  • 150 µV/m in the 88–216 MHz range,

  • 200 µV/m up to 960 MHz.

  Conducted emissions are also limited in the 0.15–30 MHz range (measured using a LISN).

  EN 55032 (which replaced CISPR 22 in Europe) is broadly aligned with these limits.

  For a PCB designer, this means that high-frequency harmonics must be suppressed. For example, the third harmonic of a 100 MHz clock (300 MHz) falls squarely within the measurement band, and its level must remain below approximately 37 dBµV/m.

  With proper PCB design (small loop areas, controlled return paths, filtering), this is achievable. Otherwise, shielding or additional mitigation measures may be required.

  
  

• IEC 61000-4-2, IEC 61000-4-3, IEC 61000-4-4, IEC 61000-4-5, and IEC 61000-4-6 define immunity test methods. Compliance is not always legally mandatory for every product, but it is typically required contractually or for CE marking (for example, under EN 55035).

  Common test levels include:

  • ESD: 8 kV

  • Radiated field: 3 V/m

  • EFT: 1 kV

  • Surge: 1 kV

  • Conducted RF: 3 V

  Applying the ESD and immunity design practices described above is intended to meet these levels. If, for example, the ADC output becomes unstable at 3 V/m, shielding and filtering should be reviewed and possibly reinforced.

  
  

• Other standards include MIL-STD-461 (military) and DO-160 (aerospace). Their requirements are significantly more stringent, but the design principles remain the same: shielding, physical separation of domains, and carefully controlled grounding.

  For example, DO-160 may require immunity to pulsed electromagnetic fields up to 600 V/m. Achieving this level of robustness typically requires a sealed metal enclosure and comprehensive filtering at all interfaces.

Key conclusion: Every PCB guideline listed above directly supports compliance with one or more EMC standards. For example, “minimizing loop area” is fundamental for FCC compliance because it reduces radiated emissions. “Adequate decoupling” is essential for CISPR-type limits because it lowers noise on the power rails. “ESD protection” is obviously required for IEC 61000-4-2 (8 kV).

During design, it is advisable to maintain an EMC checklist (such as the one outlined above) and, at the same time, clearly understand which standards the product is intended to meet. This allows prioritization of mitigation measures.

For example, in a medical device, immunity is typically more critical than the device’s own emissions. In contrast, for a radio receiver, extremely low internal noise levels are essential (e.g., CISPR 25 Class 5).

In general, however, most PCB practices are universal: good layout discipline improves both emission performance and immunity at the same time.

Conclusion and references

We have reviewed a broad set of PCB design rules aimed at ensuring electromagnetic compatibility (EMC). These guidelines address the physical behavior of electromagnetic fields—from minimizing differential current loops (reducing H-field radiation) to implementing shielding and filtering (controlling E-field and common-mode effects).

By applying these recommendations in practice, an engineer establishes the foundation for successful compliance testing and ensures reliable operation in real-world environments without causing interference to surrounding equipment.

Sources and references: The preparation of this material relied on authoritative resources, including classic EMC textbooks (Ott, Johnson), technical notes from Analog Devices and Texas Instruments, layout guidelines from manufacturers such as STMicroelectronics and Intel, as well as expert discussions on Stack Exchange and EEVblog.

Below are links to selected references: Electromagnetic Compatibility Engineering — a comprehensive reference on EMC-oriented design.

AN-139: Power Supply Layout and EMI — an example of current-loop analysis and layout impact on EMI.

Richtek Application Note: Reducing EMI in Buck Converters — practical guidance on lowering EMI in DC/DC converters.

StackExchange discussion on the benefits of a solid ground plane — explanation of EMI loop minimization principles.

Arrow / Analog Devices article on mixed-signal grounding — separation of analog and digital grounds.

TI ESD Protection Layout Guide — correct ESD protection layout practices.

Sierra Circuits: PCB Design Guidelines to Solve EMI/EMC Issues — routing and layout rules for EMC compliance.

Bruce Archambeault, Differential Signals Are NOT Immune to EMC — discussion of the importance of differential pair balance.

Regulatory limits: FCC Part 15.109 (Class B radiated limits), CISPR 25 frequency range and classification details.

Each of these references contains valuable nuances that have been summarized here. The essential point is the link between physics and implementation: by understanding why a rule works—at the level of fields and currents—you will be able to apply it correctly in new situations where simple prescriptive rules may not exist.

Below are the referenced materials in structured form:

Analog DevicesAN-139: Power Supply Layout and EMIhttps://www.analog.com/en/resources/app-notes/an-139.html

Richtek TechnologyReducing EMI in Buck Convertershttps://www.richtek.com/m/Home/Design%20Support/Technical%20Document/AN045

LearnEMCDecoupling Circuit Boards with Closely-Spaced Power Planeshttps://learnemc.com/decoupling-for-boards-with-closely-spaces-power-planes

Decoupling Circuit Boards with Widely-Spaced Power Planeshttps://learnemc.com/decoupling-for-boards-with-widely-spaced-planes

Stack ExchangeStack Exchange discussion: Reducing EMI with ground planehttps://electronics.stackexchange.com/questions/686101/reducing-emi-with-ground-plane

Sierra Circuits / ProtoExpressTips and PCB Design Guidelines for EMI & EMChttps://www.protoexpress.com/blog/7-pcb-design-tips-solve-emi-emc-issues/

IEEE EMC SocietyDesign Tipshttps://ewh.ieee.org/soc/emcs/acstrial/newsletters/summer10/DesignTips.html

AbraconCommon Mode Chokes Basics and Applicationshttps://abracon.com/uploads/resources/Common-Mode-Chokes-Basics-and-Applications.pdf

Arrow ElectronicsAnalog & Digital Grounding: Principles for Mixed-Signal Designshttps://www.arrow.com/en/research-and-events/articles/principles-of-grounding-for-mixed-signal-designs

AMD (formerly Xilinx)Analog Ground to Digital Ground Connection – UG583https://docs.amd.com/r/en-US/ug583-ultrascale-pcb-design/Analog-Ground-to-Digital-Ground-Connection

Analog Devices FAQShould the digital and analog GND planes on my board be separated?https://www.analog.com/en/resources/faqs/faq_dds_digital_and_analog_gnd_planes.html

Texas InstrumentsESD Protection Layout Guide (Rev. A)https://www.ti.com/lit/pdf/slva680

CISPR 25 overviewCISPR 25https://www.testups.com/cispr-25/

EPDT (Automotive EMI article)Understanding EMI to Make Better Informed Decisions on Switching Converters for Automotive Applicationshttps://www.epdtonthenet.net/article/199639/Understanding-EMI-to-Make-Better-Informed-Decisions-on-Switching-Converters-For-Automotive-Applications.aspx

Diodes IncorporatedDC-DC Converter Solutions Meet CISPR 25 EMI Standardshttps://www.diodes.com/design/support/cispr-25/

DigiKeyUnderstanding Electromagnetic Compatibility Standardshttps://www.digikey.com/en/articles/understanding-electromagnetic-compatibility-standards-for-switch-mode-powersupplies

U.S. FCC RegulationsFCC Part 15.109https://www.ecfr.gov/current/title-47/chapter-I/subchapter-A/part-15/subpart-B/section-15.109

These materials collectively provide theoretical background, practical layout guidance, regulatory limits, and applied case studies related to EMC-oriented PCB design.