Off-the-Shelf SEPIC Converter vs CISPR 25 Class 5: Why It Fails in Real Conditions

In this test, we decided to take a different approach and evaluate a SEPIC converter that anyone can easily buy from Amazon or AliExpress.

The idea was simple: instead of a carefully designed lab prototype, we wanted to see how a typical off-the-shelf module behaves in a real EMC environment.

The converter was tested against the CISPR 25 standard, which is considered one of the stricter EMC standards, especially for automotive applications. In practice, many electronic devices don’t pass pre-compliance testing on the first attempt when evaluated against this standard.

Picture from the web (schematic of DUT)

So here is the device we used for the test, and we evaluated it for radiated emissions inside a TEM cell.

The device was powered from a 12V lead-acid battery and configured to provide a 20V output across a 27Ω load.

The SEPIC under test

First, let’s take a look at the TEM cell noise floor without the device connected, and see how it looks in a real measurement setup.

Graph illustrating noise levels without device interference, displaying frequency ranges from 150 kHz to 100 MHz with dBμV measurements.

And here is the actual setup: the TEM cell, the spectrum analyzer, and the software used to process and accumulate the measurement data.

Actual testing setup

Now, the measurements themselves.

Since we do not currently have a rotating table, a height-adjustable antenna, or an anechoic chamber, we work with the tools we have.

In this case, we manually rotated the device around the X, Y, and Z axes and checked how the emissions changed in each position.

And this is what we found — see the measurements below.

Frequency spectrum analysis showcasing dark green trace for device position along the X-axis and light blue trace for the Y-axis alignment.

From these two measurements, it looks like the device passes the test and there is nothing to worry about.

But now let’s take a look at the Z-axis. For that, we need to place the device on its edge.

Graph displaying a light blue trace indicating device alignment along the Z-axis, accompanied by a dark green trace representing normal operation without interference.

And this is where the real trouble starts.

If we try to reduce the hot loop by adding capacitors as close as possible to the IC input and its ground, we do reduce some of the lower-frequency peaks around 1 MHz.

But at the same time, the high-frequency component around 30 MHz becomes stronger. Realistically, reducing the hot loop here is not very practical.

The reason is that this module uses two separate inductors instead of a coupled inductor. Because of that, the high-current switching path is physically spread across the board, and it becomes much harder to keep the loop compact.

As a result, the board still radiates strongly along the Z-axis, especially from the PCBA edge plane.

Attempt to reduce hot loop noise by adding capacitors to the integrated circuit, showing decreased noise levels initially, followed by an increase at higher frequencies

Now let’s look at this from the perspective of layout and signal integrity, because what we are seeing here is not random at all — it’s actually a very typical engineering trade-off.

At first, the behavior might look a bit confusing. We add capacitors close to the IC, expecting everything to get better… and part of it actually does. But at the same time, something else gets worse. This is exactly the kind of situation that shows where the real limitations of the design are.

Let’s go step by step.

When we added capacitors as close as possible to the IC input and its ground, the immediate effect was quite predictable. We reduced the impedance of the input path and, more importantly, tightened the input hot loop.

Instead of current flowing across a relatively large area of the board, it now circulates locally, right near the IC. The return path is shorter, cleaner, and more controlled. From a power integrity standpoint, this is exactly what we want.

At lower frequencies — roughly from a few hundred kHz up to a couple of MHz — this has a direct impact. In this region, the behavior is still dominated by current distribution rather than parasitic effects. So when we reduce the loop area, we directly reduce the radiated emission.

And that’s exactly what we see: the low-frequency peaks go down. No surprises here — this part behaves almost textbook-perfect.

But then we look at the higher frequencies, somewhere in the 10 to 100 MHz range, and suddenly things start going in the opposite direction.

This is where the nature of the problem changes.

At these frequencies, the capacitors we added are no longer behaving like ideal components. They are no longer just “helping” to smooth current. Instead, they become part of a much more complex high-frequency structure.

They act as very low impedance injection points for fast current pulses. Because of that, the switching edges become sharper. The di/dt increases locally, and as a result, we generate more high-frequency content.

So even though we improved the loop geometrically, we actually made the current transitions more aggressive. And in EMC, faster edges almost always mean more high-frequency noise.

There is another important effect happening at the same time.

Before adding these capacitors, the energy was distributed over a larger loop. That’s not good from a classical layout perspective, but it does have one side effect — the system is more “lossy” and less efficient at radiating.

Once we tighten the loop and reduce the impedance, we concentrate that energy into a smaller physical region. The current density increases, and the excitation of parasitic elements becomes stronger.

In other words, we didn’t remove the energy — we just moved it and made it more concentrated.

And this brings us to the PCB itself.

At tens of MHz, the board no longer behaves like a simple interconnect. Traces start acting like transmission lines. Copper planes begin to behave like antennas. Even the edges of the PCB can radiate like slot antennas if the return paths are not well controlled.

In this specific design, we don’t have a solid, continuous ground plane under the switching region. There are no stitching vias along the perimeter to contain the fields. The inductors are physically separated, so there is no magnetic field cancellation.

So when the high-frequency energy is generated — and now it is stronger and more localized — it finds an easy path to escape. And that path is very often through the edges of the PCB.

This is exactly why we see the noise increasing in the 30–100 MHz region.

The SEPIC topology itself is also part of the story.

Because the design uses two separate inductors instead of a coupled one, the magnetic fields are not cancelling each other. The energy transfer path through the coupling capacitor is physically extended, which naturally creates multiple current loops.

So even if we improve one loop, the others are still there, and at higher frequencies they start to dominate.

What’s really important to understand here is this:

We didn’t actually make the design worse.

We made it more “honest”.

By improving the low-frequency behavior, we removed part of the masking effect. The system now reveals what is really happening at higher frequencies, where parasitics and layout details dominate.

This is a very common situation in real designs. We fix power integrity at low frequencies, and suddenly RF-related problems become visible.

And this is also the point where adding more capacitors is no longer the solution.

From here on, the problem is not about bulk decoupling anymore. It’s about structure.

Things like:

• using a coupled inductor instead of two separate ones

• building a solid and continuous ground reference

• adding stitching vias to contain the fields

• controlling and shielding the switching node

Without addressing these, any further “tuning” with capacitors will just move the noise around the spectrum instead of actually reducing it.

Naturally, the next step was to add stitching vias — or at least simulate them.

Since this is a ready-made module, we can’t really modify the internal PCB, so we improvised. We used copper tape as a practical workaround.

We soldered the copper tape along the perimeter of the PCBA, tying it to the GND plane, and made sure it was pressed as tightly as possible against the board edges.

Z-axis radiated emission

And the result is quite impressive.

We end up with a much cleaner radiated emission profile — and this improvement is clearly visible not only in the X and Y orientations, but along the Z-axis as well.

However, if we compare the two cases — stitching vias alone versus stitching vias combined with capacitors on the hot loop — the capacitors still make a difference.

They do help reduce the emission further, and clearly play a positive role in improving the overall result.

Take a look at the images below — this is the case where the device is running with stitching vias only, without any additional capacitors on the hot loop.

Stitchings vias without caps on hot loop

When designing hardware, it is essential to consider EMC/EMI from the very beginning. That means understanding what is really happening at the physical level inside the device, and taking steps to avoid or at least minimize potential issues early in the design phase.

This is exactly the approach we follow in our work — building devices that operate reliably while keeping EMC/EMI problems to a minimum.

As for pre-compliance debugging, we go through the entire device in detail and identify its weak points — if they exist. And based on our experience, they always do.

And if your device doesn’t pass compliance for any reason, we can help identify the root causes and fix them.

But don’t expect quick or easy fixes — in many cases, it comes down to a proper redesign at the layout level.